Abstract:
An electrode assembly according to an exemplary embodiment of the present invention comprises: a first electrode which includes a first electrode current collector and a first electrode active material layer formed on the first electrode current collector; a second electrode which includes a second electrode current collector and a second electrode active material layer formed on the second electrode current collector; and a separator disposed between the first electrode and the second electrode. A supporting portion is formed of a groove or a protrusion at an edge of the first electrode current collector, and a combination portion is combined with the supporting portion on the first electrode active material layer.
Abstract:
An apparatus and method perform Transmit Power Control and Dynamic Frequency Selection (TPC/DFS) during a movement of a Base Station (BS). A network environment around the mobile BS is modeled. Based on the modeling result, a TPC/DFS operation scheme that is most suitable to the mobile BS is selected.
Abstract:
The present invention provides an optical film and s retardation film characterized in that each of them includes: an acrylic resin; and 20-65 parts by weight of at least two graft copolymers containing a conjugated diene-based rubber, based on 100 parts by weight of the acrylic resin, wherein at least two of the graft copolymers have different particle sizes. The present invention also provides a production method therefore.
Abstract:
Disclosed is an image sensor. The image sensor includes a semiconductor substrate including unit pixels, an interlayer dielectric layer including metal interconnections formed on the semiconductor substrate, a plurality of bottom electrodes formed on the interlayer dielectric layer in correspondence with the unit pixels, the plurality of bottom electrodes includes bottom electrodes having at least two different sizes, a photodiode formed on the interlayer dielectric layer including the bottom electrodes, and color filters formed on the photodiode in correspondence with the unit pixels.
Abstract:
A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping area surrounding the isolation area and a dielectric layer formed between the isolation layer and the first-conductivity-type doping area, wherein the first-conductivity-type doping area and the dielectric layer are located between the isolation layer and a second-conductivity-type diffusion area.
Abstract:
A method for manufacturing a CMOS image sensor is provided. The method can include forming an interlayer dielectric layer on a semiconductor substrate including a gate electrode, photodiode area, and LDD region; selectively removing the interlayer dielectric layer such that the interlayer dielectric layer remains on the photodiode area; performing a first heat treatment process; sequentially forming a first insulating layer and a second insulating layer on the semiconductor substrate, where the etching selectivity of the first insulating layer is different from the etching selectivity of the second insulating layer; selectively etching the second insulating layer to form spacers on sidewalls of the gate electrode; selectively removing the first insulating layer to expose a source/drain area and forming a high-density N-type diffusion area in the exposed source/drain area; performing a second heat treatment process; and forming a metal silicide layer the high-density N-type diffusion area.
Abstract:
Disclosed are a CMOS image sensor and a manufacturing method thereof. The present CMOS image sensor comprises: first, second, and third photo diodes and a plurality of transistors spaced at a predetermined distance in a semiconductor substrate; a diffusion blocking layer on substantially an entire surface of the substrate, including an opening therein exposing at least one of the photo diodes; an interlevel dielectric layer over the entire surface of the substrate, covering the diffusion blocking layer; first, second and third color filter layers over the interlevel dielectric layer, respectively corresponding to the first, second and third photo diodes, and a plurality of microlenses over the color filter layers, corresponding to each color filter layer.
Abstract:
An image sensor includes a first substrate having a circuitry including a wire formed therein and a photodiode formed above the circuitry. An unevenness is formed at the top of the photodiode. The unevenness may, for example, be formed by selectively etching the top of the photodiode and may act to maximize light absorption by the photodiode.
Abstract:
A CMOS image sensor and method of manufacturing the same are provided. In one embodiment, the CMOS image sensor includes: an interlayer dielectric layer formed on a semiconductor substrate including a plurality of photodiodes and transistors; a plurality of color filter isolation layers formed on the interlayer dielectric layer; a color filter layer comprising a first color filter, a second color filter, and a third color filter formed on the interlayer dielectric layer, wherein a portion of the first color filter and a portion of the second color filter are formed on one of the plurality of color filter isolation layers, and wherein a portion of the second color filter and a portion of the third color filter are formed on another of the plurality of color filter isolation layers; and microlenses formed on the color filter layer.
Abstract:
A method for fabricating a CMOS image sensor includes: forming a gate electrode on a pixel region of the semiconductor substrate and, at the same time, forming a polysilicon pattern on a middle resistor region; forming a first lightly doped n-type diffusion region on the photodiode region; forming a second lightly doped n-type diffusion region on the transistor region; consecutively forming first and second insulating layers on the entire surface of the semiconductor substrate; removing a predetermined portion of the second insulation layer on the transistor region and the middle resistor region; forming a third insulation layer on the entire surface of the semiconductor substrate; forming sidewalls of the first insulating layer and the third insulating layer on the gate electrode and the polysilicon pattern by performing an etch-back process; and heavily doping n-type impurities in the transistor region and the polysilicon pattern.