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    Decoder, method of operating the same, and apparatuses including the same
    11.
    发明授权
    Decoder, method of operating the same, and apparatuses including the same 有权
    解码器，其操作方法和包括该解码器的设备

    公开(公告)号：US08990666B2

    公开(公告)日：2015-03-24

    申请号：US13234130

    申请日：2011-09-15

    申请人： Jae Phil Kong ,  Hwa Seok Oh ,  Dong Kim

    发明人： Jae Phil Kong ,  Hwa Seok Oh ,  Dong Kim

    IPC分类号： H03M13/00 ,  G06F11/10 ,  H03M13/15

    CPC分类号： G06F11/1008 ,  G06F11/108 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1545 ,  H03M13/6502

    摘要： A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit.

    摘要翻译： 公开了解码器，解码方法及其实现方法。 在一个示例中，该方法包括从输入码字计算校正子值，使用校正子值生成关于码字的误差位置多项式，使用误差位置多项式确定码字中的误差计数，以及响应于 在码字中确定的错误计数。 在一个示例中，可以基于错误计数来确定要提供给搜索电路的时钟信号的频率，并且可以向诸如Chien搜索电路的搜索电路提供具有确定的频率的时钟信号。

    VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY
    12.
    发明申请
    VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY 审中-公开
    半导体存储器的电压调节装置

    公开(公告)号：US20130094312A1

    公开(公告)日：2013-04-18

    申请号：US13584849

    申请日：2012-08-14

    申请人： SOON-BOK JANG ,  JONG-UK SONG ,  YOUNG-WOOK KIM ,  HWA-SEOK OH

    发明人： SOON-BOK JANG ,  JONG-UK SONG ,  YOUNG-WOOK KIM ,  HWA-SEOK OH

    IPC分类号： G11C7/00 ,  H01L35/00

    CPC分类号： G11C29/021 ,  G11C7/04 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/5002

    摘要： A voltage scaling device of a semiconductor memory device, the voltage scaling device including: a delay tester for determining the number of delay cells of a delay locked loop (DLL) required to cumulatively delay a clock signal having a constant frequency, and which is input to the DLL, by one clock period; a temperature sensor for measuring the temperature of the semiconductor memory device; and a voltage regulator for regulating a supply voltage of a voltage source which provides a chip voltage to the semiconductor memory device in response to the temperature measured by the temperature sensor and a locking value corresponding to the number of delay cells calculated by the delay tester.

    摘要翻译： 一种半导体存储器件的电压调节装置，所述电压缩放装置包括：延迟测试器，用于确定累积地延迟具有恒定频率的时钟信号所需的延迟锁定环（DLL）的延迟单元数量，并且其被输入 到DLL，一个时钟周期; 温度传感器，用于测量半导体存储器件的温度; 以及电压调节器，用于响应于由温度传感器测量的温度和对应于由延迟测试器计算的延迟单元的数量的锁定值，调节向半导体存储器件提供芯片电压的电压源的电源电压。

    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME
    13.
    发明申请
    MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME 有权
    内存控制器和存储器系统，包括它们

    公开(公告)号：US20130013855A1

    公开(公告)日：2013-01-10

    申请号：US13542901

    申请日：2012-07-06

    申请人： Kui-Yon MUN ,  Hwa Seok Oh

    发明人： Kui-Yon MUN ,  Hwa Seok Oh

    IPC分类号： G06F12/00

    CPC分类号： G11C16/00 ,  G06F12/14 ,  G06F12/1408 ,  G06F12/1425 ,  G06F13/16 ,  G11C11/5642 ,  G11C16/22

    摘要： A memory controller may include a cell state generator that is configured to generate a cell state for each of a plurality of multi-level cells included in a non-volatile memory device, using data of pages. The memory controller may also include a pseudo-random number generator that is configured to generate a pseudo-random number. The memory controller may further include an operator that is configured to change the cell state of each multi-level cell using the pseudo-random number, and that is configured to output a changed cell state for each multi-level cell.

    摘要翻译： 存储器控制器可以包括单元状态发生器，其被配置为使用页面的数据来生成包括在非易失性存储器件中的多个多电平单元中的每一个的单元状态。 存储器控制器还可以包括被配置为生成伪随机数的伪随机数发生器。 存储器控制器还可以包括被配置为使用伪随机数改变每个多电平单元的单元状态并且被配置为输出每个多级单元的改变的单元状态的运算符。

    MEMORY CONTROLLER, METHOD THEREOF, AND ELECTRONIC DEVICES HAVING THE MEMORY CONTROLLER
    14.
    发明申请
    MEMORY CONTROLLER, METHOD THEREOF, AND ELECTRONIC DEVICES HAVING THE MEMORY CONTROLLER 有权
    存储器控制器，其方法和具有存储器控制器的电子设备

    公开(公告)号：US20130013854A1

    公开(公告)日：2013-01-10

    申请号：US13540078

    申请日：2012-07-02

    申请人： Kui-Yon Mun ,  Hwa Seok Oh

    发明人： Kui-Yon Mun ,  Hwa Seok Oh

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0292 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/202 ,  G06F2212/7207 ,  G11C16/0483 ,  G11C16/22 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A method for operating a memory controller is provided. The method includes generating a pseudo random number by using a seed included in a stored seed group corresponding to a page to be currently programmed, wherein the stored seed group is stored among a plurality of seed groups. Data to be programmed into the current page is randomizing by using the pseudo random number and the memory controller outputs the randomized data. A solid state drive (SSD) or other memory storage device such as a memory card includes the memory controller and includes a read only memory (ROM) storing the plurality of seed groups. The memory controller includes a micro-processor and a read only memory (ROM) storing executable code for causing the micro-processor to access the plurality of stored seed groups and to select a seed therefrom corresponding to a page to be currently programmed.

    摘要翻译： 提供了一种用于操作存储器控制器的方法。 该方法包括通过使用包含在与当前编程的页面相对应的存储的种子组中的种子来生成伪随机数，其中所存储的种子组存储在多个种子组中。 要编入当前页面的数据通过使用伪随机数进行随机化，存储器控制器输出随机数据。 固态驱动器（SSD）或诸如存储卡的其他存储器存储设备包括存储器控制器，并且包括存储多个种子组的只读存储器（ROM）。 存储器控制器包括存储可执行代码的微处理器和只读存储器（ROM），用于使微处理器访问多个存储的种子组并从其中选择与当前编程页面相对应的种子。

    Network interface card for reducing the number of interrupts and method of generating interrupts
    16.
    发明授权
    Network interface card for reducing the number of interrupts and method of generating interrupts 失效
    用于减少中断次数的网络接口卡和产生中断的方法

    公开(公告)号：US07426589B2

    公开(公告)日：2008-09-16

    申请号：US10614455

    申请日：2003-07-07

    申请人： Hwa-seok Oh

    发明人： Hwa-seok Oh

    IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F5/00

    CPC分类号： H04L49/90 ,  H04L69/16 ,  H04L69/161

    摘要： A method of generating interrupts and a network interface card, which minimizes the number of times that interrupts are generated, are provided. The method includes receiving data frames; estimating a first and second time delay and counting a number of received data frames; determining whether the first time delay has passed and generating an interrupt if the time reaches the first delay time, counting the number of data frames if the first time delay has not passed and generating the interrupt if the number of data frames is equal to N; determining whether the second time delay has passed if the number of data frames is not equal to N and generating the interrupt if the second time delay has passed; stopping operations of estimating the first and second time delays and counting the number of data frames in response to the interrupt generated, and transmitting the received data frames.

    摘要翻译： 提供了产生中断的方法和网络接口卡，其使得产生中断的次数最小化。 该方法包括接收数据帧; 估计第一和第二时间延迟并对接收到的数据帧的数量进行计数; 确定第一时间延迟是否已经过去并且如果时间达到第一延迟时间则产生中断，如果没有经过第一时间延迟则对数据帧的数量进行计数，如果数据帧的数量等于N则产生中断; 如果数据帧的数量不等于N，则确定第二时间延迟是否已经过去，并且如果第二时间延迟已经过去则产生中断; 停止对第一和第二时间延迟进行估计并响应于产生的中断对数据帧的数量进行计数，以及发送所接收的数据帧。

    Memory controllers and memory systems including the same
    19.
    发明授权
    Memory controllers and memory systems including the same 有权
    内存控制器和内存系统包括相同

    公开(公告)号：US08914572B2

    公开(公告)日：2014-12-16

    申请号：US13542901

    申请日：2012-07-06

    申请人： Kui-Yon Mun ,  Hwa Seok Oh

    发明人： Kui-Yon Mun ,  Hwa Seok Oh

    IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F13/16 ,  G11C16/00

    CPC分类号： G11C16/00 ,  G06F12/14 ,  G06F12/1408 ,  G06F12/1425 ,  G06F13/16 ,  G11C11/5642 ,  G11C16/22

    摘要： A memory controller may include a cell state generator that is configured to generate a cell state for each of a plurality of multi-level cells included in a non-volatile memory device, using data of pages. The memory controller may also include a pseudo-random number generator that is configured to generate a pseudo-random number. The memory controller may further include an operator that is configured to change the cell state of each multi-level cell using the pseudo-random number, and that is configured to output a changed cell state for each multi-level cell.

    摘要翻译： 存储器控制器可以包括单元状态发生器，其被配置为使用页面的数据来生成包括在非易失性存储器件中的多个多电平单元中的每一个的单元状态。 存储器控制器还可以包括被配置为生成伪随机数的伪随机数发生器。 存储器控制器还可以包括被配置为使用伪随机数改变每个多电平单元的单元状态并且被配置为输出每个多级单元的改变的单元状态的运算符。