公开(公告)号：US06327040B2

公开(公告)日：2001-12-04

申请号：US09793435

申请日：2001-02-26

申请人： Randhir P. S. Thakur ,  Michael Nuttall ,  J. Brett Rolfson ,  Robert James Burke

发明人： Randhir P. S. Thakur ,  Michael Nuttall ,  J. Brett Rolfson ,  Robert James Burke

IPC分类号： G01B1130

CPC分类号： G01B11/303

摘要： Disclosed is a process for analyzing the surface characteristics of opaque materials. The method comprises in one embodiment the use of a UV reflectometer to build a calibration matrix of data from a set of control samples and correlating a desired surface characteristic such as roughness or surface area to the set of reflectances of the control samples. The UV reflectometer is then used to measure the reflectances of a test sample of unknown surface characteristics. Reflectances are taken at a variety of angles of reflection for a variety of wavelengths, preferably between about 250 nanometers to about 400 nanomneters. These reflectances are then compared against the reflectances of the calibration matrix in order to correlate the closest data in the calibration matrix. By so doing, a variety of information is thereby concluded, due to the broad spectrum of wavelengths and angles of reflection used. This includes information pertaining to the roughness and surface area, as well as other surface characteristics such as grain size, grain density, grain shape, and boundary size between the grains. Surface characteristic evaluation can be conducted in-process in a manner which is non-destructive to the test sample. The method is particularly useful for determining the capacitance of highly granular polysilicon test samples used in the construction of capacitator plates in integrated circuit technology, and can be used to determine the existence of flat smooth surfaces, the presence of prismatic and hemispherical irregularities on flat smooth surfaces, and the size of such irregularities.

摘要翻译： 公开了一种用于分析不透明材料的表面特性的方法。 该方法在一个实施方案中包括使用UV反射计来构建来自一组对照样品的数据的校准矩阵，并将期望的表面特性如粗糙度或表面积与对照样品的一组反射率相关联。 然后使用UV反射计来测量未知表面特性的测试样品的反射率。 在各种各样的波长的反射角度下进行反射，优选在约250纳米至约400纳米的范围内。 然后将这些反射率与校准矩阵的反射率进行比较，以便将校准矩阵中最接近的数据相关联。 通过这样做，由于广泛的波长和使用的反射角度，从而得出各种信息。 这包括关于粗糙度和表面积的信息，以及晶粒之间的其他表面特性，例如晶粒尺寸，晶粒密度，晶粒形状和边界尺寸。 表面特性评估可以以对测试样品非破坏性的方式进行。 该方法特别有助于确定集成电路技术中用于构建电容器板的高度粒状多晶硅测试样品的电容，并且可用于确定平滑光滑表面的存在，平坦光滑的棱镜和半球形不规则的存在 表面和这种不规则的大小。

公开(公告)号：US06255228B1

公开(公告)日：2001-07-03

申请号：US09584240

申请日：2000-05-30

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： H01L2102

CPC分类号： H01L21/67051 ,  Y10S438/906

摘要： A method for removing contaminants from a semiconductor wafer having a spin on coating of material. Contaminants are removed by applying a cleaning solution to the periphery, and preferably, the exposed backside of the wafer after the edge bead has been dissolved and removed. The cleaning solution is formulated to react chemically with unwanted coating material residue to form a compound that may be ejected from the periphery of the spinning wafer. Any residual solution or precipitate that is not ejected from the wafer may be rinsed away with water, preferably deoinized water. One exemplary use of this method is the removal of metallic contaminants that may be left on the periphery and backside of a wafer after the formation of ferroelectric film coatings. A cleaning solution comprising a mixture of hydrochloric acid HCl and water H2O or ammonium hydroxide NH4OH and water H2O is applied to the periphery of the spinning wafer. The cleaning solution will react with any residual metal ions to form a metal chloride or metal hydroxide that is ejected from the wafer along with the cleaning solution.

公开(公告)号：US06187690B1

公开(公告)日：2001-02-13

申请号：US09483719

申请日：2000-01-13

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： H01L21302

CPC分类号： H01L21/67075 ,  H01L21/30604

摘要： In one aspect, the invention includes a method for manufacturing a semiconductive wafer comprising: a) providing a semiconductive material wafer having a front surface and a back surface; b) contacting the front surface with a first fluid; c) contacting the back surface with a second fluid different than the first fluid, at least one of the first and second fluids being configured to etch the semiconductive material of the wafer; at least one of the first and second fluids having a measurable component at a first concentration which is different than any concentration of said measurable component in the other of the first and second fluids; d) etching the semiconductive wafer with the at least one of the first and second fluids configured to etch the semiconductive material; and e) monitoring the measurable component concentration in at least one of the first fluid or the second fluid to ascertain if the etching has formed an opening extending completely through the substrate. In another aspect, the invention includes a method for manufacturing a semiconductive material stencil mask comprising: a) providing a semiconductive material stencil mask substrate having a front surface and a back surface; b) contacting the front surface with an inert solution having a first pH; c) contacting the back surface with an etchant having a second pH, the second pH being different than the first pH; and d) monitoring the pH of at least one of the inert solution or the etchant to ascertain if the etchant has formed an opening extending completely through the substrate.

摘要翻译： 一方面，本发明包括一种用于制造半导体晶片的方法，包括：a）提供具有前表面和后表面的半导体材料晶片; b）使前表面与第一流体接触; c）使所述后表面与不同于所述第一流体的第二流体接触，所述第一和第二流体中的至少一个被配置为蚀刻所述晶片的半导体材料; 第一和第二流体中的至少一个具有第一浓度的可测量组分，其不同于第一和第二流体中另一个中的所述可测量组分的任何浓度; d）蚀刻所述半导体晶片，所述第一和第二流体中的至少一个配置成蚀刻所述半导体材料; 以及e）监测所述第一流体或第二流体中的至少一个中的可测量的组分浓度，以确定蚀刻是否已经形成完全延伸穿过基底的开口。 另一方面，本发明包括一种用于制造半导体材料丝网掩模的方法，包括：a）提供具有前表面和后表面的半导体材料模板掩模基板; b）使前表面与具有第一pH的惰性溶液接触; c）使所述背表面与具有第二pH的蚀刻剂接触，所述第二pH不同于所述第一pH; 和d）监测惰性溶液或蚀刻剂中的至少一种的pH值，以确定蚀刻剂是否形成了完全延伸穿过基底的开口。

公开(公告)号：US06187481B1

公开(公告)日：2001-02-13

申请号：US09137662

申请日：1998-08-20

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： G03F900

CPC分类号： H01L21/3065

摘要： In one aspect, the invention includes a method of maintaining dimensions of an opening in a semiconductive material stencil mask comprising providing two different dopants within a periphery of the opening, the dopants each being provided to a concentration of at least about 1017 atoms/cm3. In another aspect, the invention includes a method of manufacturing a stencil mask from a semiconductive material comprising: a) providing a semiconductive material wafer, the wafer comprising an upper portion and a lower portion beneath the upper portion; b) forming openings extending through the upper portion of the wafer and to the lower portion of the wafer; c) forming a first dopant concentration within the wafer, the first dopant concentration being greater within the upper portion of the wafer than within at least a part of the lower portion of the wafer; d) providing a second dopant concentration within the upper portion of the wafer; and e) removing the lower portion of the wafer to leave a stencil mask substrate having openings formed therethrough. In yet another aspect, the invention comprises a semiconductive material stencil mask comprising: a) a semiconductive material substrate having an opening therethrough, the opening being defined by a periphery comprising the semiconductive material; and b) two different dopants within the semiconductive material at the periphery, the two different dopants being of a same conductivity type.

摘要翻译： 一方面，本发明包括一种在半导体材料模板掩模中保持开口的尺寸的方法，包括在开口的周边内提供两种不同的掺杂剂，所述掺杂剂各自提供至少约1017原子/ cm3的浓度。 另一方面，本发明包括从半导体材料制造模版掩模的方法，包括：a）提供半导体材料晶片，所述晶片包括在上部下方的上部和下部; b）形成延伸穿过晶片的上部和晶片下部的开口; c）在所述晶片内形成第一掺杂剂浓度，所述第一掺杂剂浓度在所述晶片的上部内比在所述晶片的下部的至少一部分内更大; d）在晶片的上部提供第二掺杂剂浓度; 以及e）去除晶片的下部以留下具有通过其形成的开口的模板掩模基板。 在另一方面，本发明包括半导体材料模板掩模，其包括：a）具有穿过其中的开口的半导体材料基板，所述开口由包括半导体材料的外围限定; 和b）外围半导体材料中的两种不同的掺杂剂，两种不同的掺杂剂具有相同的导电类型。

公开(公告)号：US6110331A

公开(公告)日：2000-08-29

申请号：US255468

申请日：1999-02-22

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： G03F1/20 ,  C25D17/00

CPC分类号： G03F1/20

摘要： A method, apparatus and system for fabricating a stencil mask for ion beam and electron beam lithography are provided. The stencil mask includes a silicon substrate, a membrane formed from the substrate, and a mask pattern formed by through openings in the membrane. The method includes defining the mask pattern and membrane area using semiconductor fabrication processes, and then forming the membrane by back side etching the substrate. The apparatus is configured to electrochemically wet etch the substrate, and to equalize pressure on either side of the substrate during the etch process. The system includes an ion implanter for defining a membrane area on the substrate, optical or e-beam pattern generators for patterning various masks on the substrate, a reactive ion etcher for etching the mask pattern in the substrate, and the apparatus for etching the back side of the substrate.

摘要翻译： 提供了用于制造用于离子束和电子束光刻的模板掩模的方法，装置和系统。 模板掩模包括硅衬底，由衬底形成的膜，以及由膜中的通孔开口形成的掩模图案。 该方法包括使用半导体制造工艺限定掩模图案和膜面积，然后通过背面蚀刻基板形成膜。 该设备被配置为电化学湿法蚀刻衬底，并且在蚀刻工艺期间平衡衬底的任一侧上的压力。 该系统包括用于限定衬底上的膜区域的离子注入机，用于在衬底上构图各种掩模的光束或电子束图案发生器，用于蚀刻衬底中的掩模图案的反应离子蚀刻器和用于蚀刻背面的设备 侧面。

公开(公告)号：US6072226A

公开(公告)日：2000-06-06

申请号：US844169

申请日：1997-04-18

申请人： Randhir P. S. Thakur ,  J. Brett Rolfson ,  Fernando Gonzalez ,  John T. Moore

发明人： Randhir P. S. Thakur ,  J. Brett Rolfson ,  Fernando Gonzalez ,  John T. Moore

IPC分类号： H01L21/3105 ,  H01L21/316 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/31053 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31658 ,  H01L21/76216 ,  Y10S438/978

摘要： A method for forming a field isolation structure and an improved field isolation structure are provided. The method includes forming a field oxide on a silicon substrate using an ozone enhanced local oxidation of silicon (LOCOS) process. Following formation of the field oxide a surface topography of the field oxide is sloped or tapered by ion milling, dry etching, reactive ion etching or chemical mechanical planarization. With an ozone enhanced LOCOS process, oxidation rates are increased and stress between the field oxide and substrate are reduced. This permits the formation of field isolation structures with reduced lateral encroachment and a smaller bird's beak area. In addition, the sloped topography of the field oxide permits a subsequently deposited conductive layer (e.g., polysilicon) to be etched without the formation of conductive stringers. During the etch process the active areas on the substrate can be protected with a sacrificial oxide or by only partially removing the LOCOS mask.

摘要翻译： 提供了一种用于形成场隔离结构和改进的场隔离结构的方法。 该方法包括使用臭氧增强的局部氧化硅（LOCOS）工艺在硅衬底上形成场氧化物。 在形成场氧化物之后，场氧化物的表面形貌通过离子研磨，干蚀刻，反应离子蚀刻或化学机械平面化而倾斜或渐缩。 通过臭氧增强的LOCOS工艺，氧化速率增加，场氧化物和衬底之间的应力降低。 这允许形成具有减小的横向侵入和较小鸟喙面积的场隔离结构。 此外，场氧化物的倾斜形貌允许随后沉积的导电层（例如，多晶硅）被蚀刻而不形成导电桁条。 在蚀刻过程中，可以用牺牲氧化物或仅部分去除LOCOS掩模来保护衬底上的有源区域。

公开(公告)号：US6025278A

公开(公告)日：2000-02-15

申请号：US916818

申请日：1997-08-22

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： H01L21/00 ,  H01L21/306

CPC分类号： H01L21/67075 ,  H01L21/30604

摘要： In one aspect, the invention includes a method for manufacturing a semiconductive wafer comprising: a) providing a semiconductive material wafer having a front surface and a back surface; b) contacting the front surface with a first fluid; c) contacting the back surface with a second fluid different than the first fluid, at least one of the first and second fluids being configured to etch the semiconductive material of the wafer; at least one of the first and second fluids having a measurable component at a first concentration which is different than any concentration of said measurable component in the other of the first and second fluids; d) etching the semiconductive wafer with the at least one of the first and second fluids configured to etch the semiconductive material; and e) monitoring the measurable component concentration in at least one of the first fluid or the second fluid to ascertain if the etching has formed an opening extending completely through the substrate. In another aspect, the invention includes a method for manufacturing a semiconductive material stencil mask comprising: a) providing a semiconductive material stencil mask substrate having a front surface and a back surface; b) contacting the front surface with an inert solution having a first pH; c) contacting the back surface with an etchant having a second pH, the second pH being different than the first pH; and d) monitoring the pH of at least one of the inert solution or the etchant to ascertain if the etchant has formed an opening extending completely through the substrate.

摘要翻译： 一方面，本发明包括一种用于制造半导体晶片的方法，包括：a）提供具有前表面和后表面的半导体材料晶片; b）使前表面与第一流体接触; c）使所述后表面与不同于所述第一流体的第二流体接触，所述第一和第二流体中的至少一个被配置为蚀刻所述晶片的半导体材料; 第一和第二流体中的至少一个具有第一浓度的可测量组分，其不同于第一和第二流体中另一个中的所述可测量组分的任何浓度; d）蚀刻所述半导体晶片，所述第一和第二流体中的至少一个配置成蚀刻所述半导体材料; 以及e）监测所述第一流体或第二流体中的至少一个中的可测量的组分浓度，以确定蚀刻是否已经形成完全延伸穿过基底的开口。 另一方面，本发明包括一种用于制造半导体材料丝网掩模的方法，包括：a）提供具有前表面和后表面的半导体材料模板掩模基板; b）使前表面与具有第一pH的惰性溶液接触; c）使所述背表面与具有第二pH的蚀刻剂接触，所述第二pH不同于所述第一pH; 和d）监测惰性溶液或蚀刻剂中的至少一种的pH值，以确定蚀刻剂是否形成了完全延伸穿过基底的开口。

公开(公告)号：US6013943A

公开(公告)日：2000-01-11

申请号：US850461

申请日：1997-05-05

申请人： David A. Cathey ,  J. Brett Rolfson ,  Valerie A. Ward ,  Karen M. Winchester

发明人： David A. Cathey ,  J. Brett Rolfson ,  Valerie A. Ward ,  Karen M. Winchester

IPC分类号： H01L21/311 ,  H01L21/318 ,  H01L23/58

CPC分类号： H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

摘要： A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH.sub.3 flow, decreasing the SiH.sub.4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.

摘要翻译： 用于氧化硅干氟蚀刻工艺中的蚀刻停止层由氮化物制成，其中以氢键连接在其中，其形式为N-H键，O-H键或截留的游离氢。 蚀刻停止层是通过在标准PECVD氮化硅制造工艺中增加NH 3流，降低SiH4流量，降低氮气流量或全部三种来制备的。 替代地，蚀刻停止可以通过在PECVD工艺或LPCVD工艺中脉冲RF场来制造。

公开(公告)号：US6001189A

公开(公告)日：1999-12-14

申请号：US724578

申请日：1996-09-30

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： B08B3/04 ,  B08B3/14 ,  H01L21/00 ,  H01L21/306 ,  C02F1/20

CPC分类号： H01L21/02052 ,  B01D19/0036 ,  B01D19/0068 ,  B08B3/04 ,  B08B3/14 ,  H01L21/67057 ,  H01L21/67086 ,  Y10S134/902 ,  Y10S438/906

摘要： A method for wet processing of a semiconductor-containing substrate that reduces contamination in the wet process by removing undesired sources of gas contamination, the method comprising: pumping a processing liquid through a degasifier, exposing the semiconductor wafer, in a vessel, to the degasified processing liquid; and optionally recirculating the processing liquid through the degasifier and back into the vessel.

公开(公告)号：US5804336A

公开(公告)日：1998-09-08

申请号：US696173

申请日：1996-08-13

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： G03F1/00 ,  G03F1/26 ,  G03F1/32 ,  G03F9/00

CPC分类号： G03F1/32 ,  G03F1/26

摘要： The present invention provides a method of fabricating photomasks having a border region and a pattern region, which may be electrically isolated. The border region may include a nontransparent region, such as an opaque chrome layer. The pattern region may include a substantially nontransparent region, such as a leaky chrome layer. The methods of the present invention include placing the photomask in an electrochemical cell and electrically connecting a portion of the photomask to an electrode, and applying a potential, thereby electrochemically transferring a layer between the electrochemical cell and the photomask.

摘要翻译： 本发明提供一种制造具有边界区域和图案区域的光掩模的方法，其可以是电隔离的。 边界区域可以包括不透明区域，例如不透明铬层。 图案区域可以包括基本不透明的区域，例如渗漏铬层。 本发明的方法包括将光掩模放置在电化学电池中并将光掩模的一部分电连接到电极，并施加电位，从而在电化学电池和光掩模之间电化学转移一层。