公开(公告)号：US06218690B1

公开(公告)日：2001-04-17

申请号：US09376041

申请日：1999-08-16

Applicant: Hyoung-sub Kim ,  Ja-hum Ku ,  Chul-sung Kim ,  Jung-woo Park

Inventor： Hyoung-sub Kim ,  Ja-hum Ku ,  Chul-sung Kim ,  Jung-woo Park

IPC: H01L2976

CPC classification number: H01L29/66606 ,  H01L29/66621

Abstract: A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the semiconductor substrate, the drain being positioned a predetermined distance from the source. A silicide film is formed on the source and the drain. Insulative film spacers are formed on sidewalls of a trench, the trench being formed by etchin the semiconductor substrate between the source and the drain. A gate insulative film is formed on a lower portion of the trench and a metal gate is formed on the gate insulative film between the insulative film spacers. The metal gate is electrically isolated from the source and the drain by the insulative film spacers.

Abstract translation: 提供了反向自对准场效应晶体管及其制造方法。 反向自对准晶体管包括形成在半导体衬底的有源区上的源极和形成在半导体衬底的有源区上的漏极，漏极位于与源极预定的距离处。 在源极和漏极上形成硅化物膜。 绝缘膜间隔物形成在沟槽的侧壁上，沟槽通过蚀刻在源极和漏极之间的半导体衬底形成。 栅极绝缘膜形成在沟槽的下部，并且在绝缘膜间隔物上的栅极绝缘膜上形成金属栅极。 金属栅极通过绝缘膜间隔物与源极和漏极电隔离。

公开(公告)号：US09613002B2

公开(公告)日：2017-04-04

申请号：US14067474

申请日：2013-10-30

Applicant: Chang-Ho Han ,  Dae-Wook Kim ,  Jin-Young Lee ,  Sung-Won Choi ,  Byoung-Hoon Kim ,  Han-Hum Park ,  Sang-Jin Choi ,  Ja-Hum Ku

Inventor： Chang-Ho Han ,  Dae-Wook Kim ,  Jin-Young Lee ,  Sung-Won Choi ,  Byoung-Hoon Kim ,  Han-Hum Park ,  Sang-Jin Choi ,  Ja-Hum Ku

IPC: G01N37/00 ,  G06F17/18 ,  H01L21/66 ,  G03F7/20

CPC classification number: G06F17/18 ,  G03F7/70633 ,  H01L22/00 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A processing method includes processing a wafer based on initial data, measuring errors for each of the plurality of areas, calculating an error similarity of at least some of the plurality of areas as a function of a separation distance between each pair of some of the areas, selecting a first area and a plurality of second areas adjacent to the first area, calculating weight values for the second areas based on the error similarities between each pair of second areas and the error similarities between the first area and each second area, calculating an estimated error of the first area based on the measured errors of the second areas and the weight values for the second areas, and generating estimated data based on the estimated errors for each of the plurality of areas.

公开(公告)号：US09508727B2

公开(公告)日：2016-11-29

申请号：US14853442

申请日：2015-09-14

Applicant: Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

Inventor： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC: H01L21/336 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Abstract translation: 一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极 线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。

公开(公告)号：US20140229134A1

公开(公告)日：2014-08-14

申请号：US14067474

申请日：2013-10-30

Applicant: Chang-Ho Han ,  DAE-WOOK KIM ,  JIN-YOUNG LEE ,  SUNG-WON CHOI ,  BYOUNG-HOON KIM ,  HAN-HUM PARK ,  SANG-JIN CHOI ,  JA-HUM KU

Inventor： Chang-Ho Han ,  DAE-WOOK KIM ,  JIN-YOUNG LEE ,  SUNG-WON CHOI ,  BYOUNG-HOON KIM ,  HAN-HUM PARK ,  SANG-JIN CHOI ,  JA-HUM KU

IPC: G06F17/18 ,  H01L21/66

CPC classification number: G06F17/18 ,  G03F7/70633 ,  H01L22/00 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A processing method includes processing a wafer based on initial data, measuring errors for each of the plurality of areas, calculating an error similarity of at least some of the plurality of areas as a function of a separation distance between each pair of some of the areas, selecting a first area and a plurality of second areas adjacent to the first area, calculating weight values for the second areas based on the error similarities between each pair of second areas and the error similarities between the first area and each second area, calculating an estimated error of the first area based on the measured errors of the second areas and the weight values for the second areas, and generating estimated data based on the estimated errors for each of the plurality of areas.

Abstract translation: 一种处理方法包括：基于初始数据处理晶片，测量多个区域中的每个区域的误差，计算多个区域中的至少一些区域的误差相似度，作为每对区域之间的间隔距离的函数 ，选择与所述第一区域相邻的第一区域和多个第二区域，基于每对第二区域之间的误差相似度和所述第一区域与每个第二区域之间的误差相似度来计算所述第二区域的权重值， 基于第二区域的测量误差和第二区域的权重值对第一区域的估计误差，以及基于多个区域中的每一个的估计误差生成估计数据。

公开(公告)号：US07816271B2

公开(公告)日：2010-10-19

申请号：US11778039

申请日：2007-07-14

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  WanJae Park ,  Chong Kwang Chang ,  Theodorus E. Standaert

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  WanJae Park ,  Chong Kwang Chang ,  Theodorus E. Standaert

IPC: H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823871

Abstract: Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.

Abstract translation: 提供了在DSL（双应力衬垫）半导体器件中形成通孔接触的半导体制造方法，其中实现改进的蚀刻工艺流程，以便能够通过双应力衬垫结构的重叠和非重叠区域蚀刻通孔接触开口以暴露 底层的水银触点和其他设备触点，同时减轻或消除缺陷机制，例如对DSL的非重叠区域下的接触区域进行过蚀刻。

公开(公告)号：US07790622B2

公开(公告)日：2010-09-07

申请号：US11778038

申请日：2007-07-14

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  Jun Jung Kim ,  Chong Kwang Chang ,  Min-Chul Sun ,  Jong Ho Yang ,  Thomas W. Dyer

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  Jun Jung Kim ,  Chong Kwang Chang ,  Min-Chul Sun ,  Jong Ho Yang ,  Thomas W. Dyer

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.

Abstract translation: 提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制​​或以其它方式阻碍或限制后续工艺流程。

公开(公告)号：US07781276B2

公开(公告)日：2010-08-24

申请号：US12353519

申请日：2009-01-14

Applicant: Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

Inventor： Kyoung-woo Lee ,  Ja-hum Ku ,  Seung-man Choi

IPC: H01L21/337

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

Abstract translation: CMOS集成电路在其中具有NMOS和PMOS晶体管，并且在NMOS晶体管上延伸绝缘层。 提供绝缘层以向NMOS晶体管施加相对较大的拉伸应力。 特别地，绝缘层被形成为具有足够高的内部应力特性，其在NMOS晶体管的沟道区域中赋予约2千兆帕（2GPa）至约4千兆帕（4GPa）的范围内的拉伸应力。

公开(公告)号：US20090250752A1

公开(公告)日：2009-10-08

申请号：US12457323

申请日：2009-06-08

Applicant: Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

Inventor： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC: H01L29/94 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

Abstract translation: 提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。 覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。 封盖层允许使用选择性氧化工艺，其可以是在富H2气氛中使用H 2 O和H 2的分压的湿式氧化工艺，以氧化基板和金属栅极图案的部分，同时抑制 可以包括在金属栅极图案中的金属层的氧化。 这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

公开(公告)号：US20090017625A1

公开(公告)日：2009-01-15

申请号：US11778038

申请日：2007-07-14

Applicant: Kyoung Woo Lee ,  Ja Hum Ku ,  JunJung Kim ,  Chong Kwang Chang ,  Min-Chul Sun ,  Jong Ho Yang ,  Thomas W. Dyer

Inventor： Kyoung Woo Lee ,  Ja Hum Ku ,  JunJung Kim ,  Chong Kwang Chang ,  Min-Chul Sun ,  Jong Ho Yang ,  Thomas W. Dyer

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.

Abstract translation: 提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制​​或以其它方式阻碍或限制后续工艺流程。

公开(公告)号：US07465617B2

公开(公告)日：2008-12-16

申请号：US11269599

申请日：2005-11-09

Applicant: Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

Inventor： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L27/115

Abstract: A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

Abstract translation: 提供一种制造包括双间隔件的半导体器件的方法。 可以通过供应氮源气体在反应室中产生和保持氮气氛。 然后可以将硅源气体和氧源气体供应到反应室以在可包括导电材料层的半导体衬底上沉积氧化硅层。 然后可以通过执行一般CVD工艺在氧化硅层上形成氮化硅层。 接下来，可以蚀刻氮化硅层直到氧化硅层露出。 由于氮化硅和氧化硅之间的蚀刻选择性的差异，氮化硅层的部分可能残留在导电材料层的侧壁上。 结果，可以在侧壁上形成由氧化硅层和氮化硅层形成的双重间隔物。