公开(公告)号：US09384837B2

公开(公告)日：2016-07-05

申请号：US14467920

申请日：2014-08-25

申请人： Hyun-Wook Park ,  Kitae Park ,  Jaeyong Jeong

发明人： Hyun-Wook Park ,  Kitae Park ,  Jaeyong Jeong

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC分类号： G11C16/14 ,  G11C11/56 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445

摘要： An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.

摘要翻译： 一种操作包括多个存储器单元的存储器系统的方法包括：根据第二操作模式，改变基于第一操作模式操作的至少一些存储器单元的操作模式; 并且当操作模式改变时，基于改变擦除条件，对在其中改变操作模式的存储单元执行改变擦除操作。 当存储单元在第一操作模式下工作时，基于第一擦除条件执行正常擦除操作，并且当存储器单元在第二操作模式下操作时，基于第二擦除条件执行正常擦除操作。 改变擦除条件不同于第一和第二擦除条件中的至少一个。

公开(公告)号：US20140369124A1

公开(公告)日：2014-12-18

申请号：US14287580

申请日：2014-05-27

申请人： Sangkwon MOON ,  Kyung Ho KIM ,  Jihong KIM ,  Jaeyong JEONG

发明人： Sangkwon MOON ,  Kyung Ho KIM ,  Jihong KIM ,  Jaeyong JEONG

IPC分类号： G11C16/16 ,  G11C16/26

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/26 ,  G11C16/349

摘要： A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based on the determined erase mode.

摘要翻译： 一种操作存储器件的方法包括：基于对存储器块执行的擦除次数和用于执行每个擦除周期的擦除电压来确定擦除模式; 以及基于所确定的擦除模式，设置用于对所述存储器块执行擦除操作的擦除电压电平。

公开(公告)号：US20130021852A1

公开(公告)日：2013-01-24

申请号：US13552668

申请日：2012-07-19

申请人： JAEYONG JEONG

发明人： JAEYONG JEONG

IPC分类号： G11C7/10

CPC分类号： G11C16/28 ,  G11C16/0483 ,  G11C16/20

摘要： A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array storing setup data and reference data, and first and second latch units respectively configured to store the setup data and the reference data sensed from the memory cell array upon a power-up of the memory system. The controller is configured to control a sensing operation of the nonvolatile memory. An operating environment of the nonvolatile memory is determined by the setup data stored in the first latch unit, and the controller controls the nonvolatile memory to re-store the setup data of the memory cell array in the first latch unit when the reference data of the second latch unit is changed.

摘要翻译： 存储器系统包括非易失性存储器和控制器。 非易失性存储器包括存储设置数据和参考数据的存储单元阵列，以及第一和第二锁存单元，分别被配置为在存储器系统的加电时存储从存储单元阵列感测的建立数据和参考数据。 控制器被配置为控制非易失性存储器的感测操作。 非易失性存储器的操作环境由存储在第一锁存单元中的设置数据确定，并且当第一锁存单元的参考数据为“0”时，控制器控制该非易失性存储器以将存储单元阵列的建立数据重新存储在第一锁存单元中 第二锁存单元被改变。

公开(公告)号：US09646705B2

公开(公告)日：2017-05-09

申请号：US14287580

申请日：2014-05-27

申请人： Sangkwon Moon ,  Kyung Ho Kim ,  Jihong Kim ,  Jaeyong Jeong

发明人： Sangkwon Moon ,  Kyung Ho Kim ,  Jihong Kim ,  Jaeyong Jeong

IPC分类号： G11C16/16 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/26 ,  G11C16/349

摘要： A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based on the determined erase mode.

公开(公告)号：US20150103597A1

公开(公告)日：2015-04-16

申请号：US14467920

申请日：2014-08-25

申请人： HYUN-WOOK PARK ,  KITAE PARK ,  JAEYONG JEONG

发明人： HYUN-WOOK PARK ,  KITAE PARK ,  JAEYONG JEONG

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C11/56 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445

摘要： An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.

摘要翻译： 一种操作包括多个存储器单元的存储器系统的方法包括：根据第二操作模式，改变基于第一操作模式操作的至少一些存储器单元的操作模式; 并且当操作模式改变时，基于改变擦除条件，对在其中改变操作模式的存储单元执行改变擦除操作。 当存储单元在第一操作模式下工作时，基于第一擦除条件执行正常擦除操作，并且当存储器单元在第二操作模式下操作时，基于第二擦除条件执行正常擦除操作。 改变擦除条件不同于第一和第二擦除条件中的至少一个。

公开(公告)号：US08976595B2

公开(公告)日：2015-03-10

申请号：US13526794

申请日：2012-06-19

申请人： Jaeyong Jeong ,  Ju Seok Lee

发明人： Jaeyong Jeong ,  Ju Seok Lee

IPC分类号： G11C16/00 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/3454

摘要： A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.

摘要翻译： 非易失性存储器件包括连接到全位线结构中的多个位线的单元阵列，连接到多个位线的寻址缓冲器电路以及被配置为控制页缓冲器电路的控制逻辑。 控制逻辑控制页面缓冲电路以在第一读取模式中感测与选定页面的偶数和偶数列对应的存储器单元，并且读取对应于偶数和奇数列之一的存储器单元 的第二读取模式。 在第一读取模式下执行感测操作至少两次，并且在第二读取模式中执行一次感测操作。

公开(公告)号：US08705294B2

公开(公告)日：2014-04-22

申请号：US13552668

申请日：2012-07-19

申请人： Jaeyong Jeong

发明人： Jaeyong Jeong

IPC分类号： G11C16/04

CPC分类号： G11C16/28 ,  G11C16/0483 ,  G11C16/20

摘要： A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array storing setup data and reference data, and first and second latch units respectively configured to store the setup data and the reference data sensed from the memory cell array upon a power-up of the memory system. The controller is configured to control a sensing operation of the nonvolatile memory. An operating environment of the nonvolatile memory is determined by the setup data stored in the first latch unit, and the controller controls the nonvolatile memory to re-store the setup data of the memory cell array in the first latch unit when the reference data of the second latch unit is changed.

摘要翻译： 存储器系统包括非易失性存储器和控制器。 非易失性存储器包括存储设置数据和参考数据的存储单元阵列，以及第一和第二锁存单元，分别被配置为在存储器系统的加电时存储从存储单元阵列感测的建立数据和参考数据。 控制器被配置为控制非易失性存储器的感测操作。 非易失性存储器的操作环境由存储在第一锁存单元中的设置数据确定，并且当第一锁存单元的参考数据为“0”时，控制器控制该非易失性存储器以将存储单元阵列的建立数据重新存储在第一锁存单元中 第二锁存单元被改变。

公开(公告)号：US20130117634A1

公开(公告)日：2013-05-09

申请号：US13604772

申请日：2012-09-06

申请人： Sang-Hyun JOO ,  Kitae PARK ,  Sangyong YOON ,  Jaeyong JEONG

发明人： Sang-Hyun JOO ,  Kitae PARK ,  Sangyong YOON ,  Jaeyong JEONG

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048 ,  G06F3/0649 ,  G06F11/1068 ,  G06F11/14 ,  G06F11/1402 ,  G06F12/0246 ,  G06F2212/72 ,  G06F2212/7205 ,  G11C29/42 ,  G11C2211/5641 ,  H03M13/05 ,  H03M13/3715

摘要： A memory system comprises a nonvolatile memory device comprising a memory cell array comprising first and second memory blocks, and a memory controller configured to control the nonvolatile memory device to read data from the first memory block, selectively determine an error correction operation to be performed on the data after it is read from the first memory block based on a state of at least one of the first and second memory blocks, and then store the data in the second memory block.

摘要翻译： 存储器系统包括非易失性存储器件，其包括包括第一和第二存储器块的存储器单元阵列，以及存储器控制器，其被配置为控制非易失性存储器件从第一存储器块读取数据，选择性地确定要执行的纠错操作 基于第一和第二存储器块中的至少一个的状态从第一存储器块读取之后的数据，然后将数据存储在第二存储器块中。