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公开(公告)号：US08089797B2
公开(公告)日：2012-01-03
申请号：US12659515
申请日：2010-03-11
申请人： Ho-jung Kim , Jai-kwang Shin , Sun-ae Seo , Sung-chul Lee
发明人： Ho-jung Kim , Jai-kwang Shin , Sun-ae Seo , Sung-chul Lee
IPC分类号： G11C19/00
CPC分类号： G11C19/0808 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.
摘要翻译： 存储单元包括：存储单元阵列单元，具有垂直地布置在基板上的多个纳米线，所述多个纳米线中的每一个具有用于存储信息的多个域; 形成在所述基板上并被配置为选择所述多个纳米线中的至少一个的纳米线选择单元; 域移动控制单元，形成在所述基板上，并且被配置为控制相对于所述多个纳米线中的至少一个的域移动操作; 以及读/写控制单元，形成在所述基板上并被配置为控制关于所述多根纳米线中的至少一个的读取操作和写入操作中的至少一个。
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12.发明申请High electron mobility transistors exhibiting dual depletion and methods of manufacturing the same 有权显示出双耗尽的高电子迁移率晶体管及其制造方法公开(公告)号：US20110215378A1
公开(公告)日：2011-09-08
申请号：US12929492
申请日：2011-01-28
申请人： In-Jun Hwang , Jong-Seob Kim , Hyuk-Soon Choi , Ki-Ha Hong , Jai-Kwang Shin , Jae-Joon Oh
发明人： In-Jun Hwang , Jong-Seob Kim , Hyuk-Soon Choi , Ki-Ha Hong , Jai-Kwang Shin , Jae-Joon Oh
IPC分类号： H01L29/778
CPC分类号： H01L29/66462 , H01L29/0657 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/7783 , H01L29/7786
摘要： High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer.
摘要翻译： 表现出双重缺陷的高电子迁移率晶体管（HEMT）及其制造方法。 HEMT包括设置在具有不同极性的多个半导体层上的源电极，栅极电极和漏电极。 在源电极和漏电极之间存在双耗尽区。 多个半导体层包括上材料层，中间材料层和下材料层，并且中间材料层的极性与上材料层和下材料层的极性不同。
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公开(公告)号：US07999474B2
公开(公告)日：2011-08-16
申请号：US12585972
申请日：2009-09-30
IPC分类号： H01J17/49
摘要： A plasma-discharge light emitting device is provided. The plasma-discharge light emitting device may include: rear and front panels separated from each other in a predetermined interval, wherein at least one discharge cell may be provided between the rear and front panels, and wherein plasma discharge may be generated in the discharge cells; a pair of discharge electrodes provided on at least one of the rear and front panels for each of the discharge cells; a trench provided as a portion of each of the discharge cells between the pair of the discharge electrodes; and electron-emitting material layers provided on both sidewalls of the trench.
摘要翻译： 提供了一种等离子体放电发光器件。 等离子体放电发光器件可以包括：以预定间隔彼此分开的后面板和前面板，其中可以在后面板和前面板之间设置至少一个放电单元，并且其中可以在放电单元中产生等离子体放电 ; 一对放电电极，设置在每个放电单元的后面板和前面板中的至少一个上; 设置在所述一对放电电极之间的每个放电单元的一部分的沟槽; 以及设置在沟槽的两个侧壁上的电子发射材料层。
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公开(公告)号：US07977707B2
公开(公告)日：2011-07-12
申请号：US12005399
申请日：2007-12-27
申请人： Ki-ha Hong , Jae-woong Hyun , Young-gu Jin , Jai-kwang Shin
发明人： Ki-ha Hong , Jae-woong Hyun , Young-gu Jin , Jai-kwang Shin
IPC分类号： H01L33/00
CPC分类号： H01L27/108 , H01L27/10802 , H01L29/7841
摘要： Provided are a capacitorless DRAM and methods of manufacturing the same. The capacitorless DRAM may include a substrate including a source, a drain and a channel, a gate on the channel of the substrate, and a hole reserving unit below the channel.
摘要翻译： 提供了一种无电容器DRAM及其制造方法。 无电容器DRAM可以包括基板，包括源极，漏极和沟道，基板通道上的栅极，以及沟道下方的孔保留单元。
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公开(公告)号：US07955562B2
公开(公告)日：2011-06-07
申请号：US12385284
申请日：2009-04-03
申请人： Ki-ha Hong , Hyuk-soon Choi , Jong-seob Kim , Jai-kwang Shin
发明人： Ki-ha Hong , Hyuk-soon Choi , Jong-seob Kim , Jai-kwang Shin
CPC分类号： G01N29/036 , G01N2291/0257 , Y10S977/957
摘要： Provided is a chemical sensor that may include a first electrode on a substrate, a sensing member covering the first electrode on the substrate, and a plurality of second electrodes on a surface of the sensing member exposing the surface of the sensing member. The chemical sensor may be configured to measure the change in electrical characteristics when a compound to be sensed is adsorbed on the sensing member. Provided also is a chemical sensor array including an array of chemical sensors.
摘要翻译： 提供了一种化学传感器，其可以包括在基板上的第一电极，覆盖基板上的第一电极的感测构件和暴露感测构件的表面的感测构件的表面上的多个第二电极。 化学传感器可以被配置为当要感测的化合物吸附在感测构件上时测量电特性的变化。 还提供了包括化学传感器阵列的化学传感器阵列。
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16.发明申请Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit 有权非易失性逻辑电路，包括非易失性逻辑电路的集成电路和操作集成电路的方法公开(公告)号：US20110122709A1
公开(公告)日：2011-05-26
申请号：US12801502
申请日：2010-06-11
申请人： Ho-jung Kim , Jai-kwang Shin , Kwang-seok Kim , Kee-won Kim
发明人： Ho-jung Kim , Jai-kwang Shin , Kwang-seok Kim , Kee-won Kim
IPC分类号： G11C7/10 , H03K19/173
CPC分类号： H03K19/1733 , G11C14/0054 , G11C14/0081 , G11C14/009 , H03K3/356008
摘要： A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory cells according to a direction of a current flowing through the first and second nonvolatile memory cells when a write enable signal is activated. The direction of flow of current determined based on data on the respective first and second latch nodes, and a logic value written on the first nonvolatile memory cells is different from a logic value written on the second nonvolatile memory cell.
摘要翻译： 非易失性逻辑电路包括：锁存单元，包括一对第一和第二锁存节点; 以及分别电连接到第一和第二锁存节点的一对第一和第二非易失性存储单元。 当写入使能信号被激活时，根据流过第一和第二非易失性存储器单元的电流的方向在第一和第二非易失性存储器单元上执行写入操作。 基于相应的第一和第二锁存节点上的数据确定的电流的流动方向和写在第一非易失性存储器单元上的逻辑值与写入第二非易失性存储单元的逻辑值不同。
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公开(公告)号：US20110121409A1
公开(公告)日：2011-05-26
申请号：US12923240
申请日：2010-09-10
申请人： David Seo , Jai-kwang Shin , Sun-ae Seo
发明人： David Seo , Jai-kwang Shin , Sun-ae Seo
IPC分类号： H01L29/78 , H01L21/314 , H01L21/336
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/02269 , H01L21/0237 , H01L21/02444 , H01L21/02527 , H01L21/0262 , H01L21/02631 , H01L29/1606 , H01L29/4908 , H01L29/66742 , H01L29/78603 , H01L29/78681 , H01L29/78684
摘要： Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10−11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.
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公开(公告)号：US07910913B2
公开(公告)日：2011-03-22
申请号：US12000641
申请日：2007-12-14
申请人： Hyuk-soon Choi , Ji-hyun Hur , Yoon-ho Kang , Hyo-sug Lee , Jai-kwang Shin , Jae-joon Oh
发明人： Hyuk-soon Choi , Ji-hyun Hur , Yoon-ho Kang , Hyo-sug Lee , Jai-kwang Shin , Jae-joon Oh
IPC分类号： H01L47/00
CPC分类号： H01L45/1246 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10T29/49002
摘要： A phase change memory device includes a switching device and a storage node connected to the switching device. The storage node includes a bottom stack, a phase change layer disposed on the bottom stack and a top stack disposed on the phase change layer. The phase change layer includes a unit for increasing a path of current flowing through the phase change layer and reducing a volume of a phase change memory region. The area of a surface of the unit disposed opposite to the bottom stack is greater than or equal to the area of a surface of the bottom stack in contact with the phase change layer.
摘要翻译： 相变存储器件包括开关器件和连接到开关器件的存储节点。 存储节点包括底部堆叠，设置在底部堆叠上的相变层和设置在相变层上的顶部堆叠。 相变层包括用于增加流过相变层的电流的路径并减小相变存储区的体积的单元。 与底部叠层相对设置的单元的表面的面积大于或等于与相变层接触的底部叠层的表面的面积。
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公开(公告)号：US20110063885A1
公开(公告)日：2011-03-17
申请号：US12659515
申请日：2010-03-11
申请人： Ho-jung Kim , Jai-kwang Shin , Sun-ae Seo , Sung-chul Lee
发明人： Ho-jung Kim , Jai-kwang Shin , Sun-ae Seo , Sung-chul Lee
CPC分类号： G11C19/0808 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.
摘要翻译： 存储单元包括：存储单元阵列单元，具有垂直地布置在基板上的多个纳米线，所述多个纳米线中的每一个具有用于存储信息的多个域; 形成在所述基板上并被配置为选择所述多个纳米线中的至少一个的纳米线选择单元; 域移动控制单元，形成在所述基板上，并且被配置为控制相对于所述多个纳米线中的至少一个的域移动操作; 以及读/写控制单元，形成在所述基板上并被配置为控制关于所述多根纳米线中的至少一个的读取操作和写入操作中的至少一个。
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20.发明申请Magnetic tracks, information storage devices including magnetic tracks, and methods of operating information storage devices 失效磁迹，包括磁迹的信息存储设备，以及操作信息存储设备的方法公开(公告)号：US20100149863A1
公开(公告)日：2010-06-17
申请号：US12461062
申请日：2009-07-30
申请人： Sung-chul Lee , Jai-kwang Shin , Sun-ae Seo , Young-jin Cho , Ung-hwan Pl , Ji-young Bae
发明人： Sung-chul Lee , Jai-kwang Shin , Sun-ae Seo , Young-jin Cho , Ung-hwan Pl , Ji-young Bae
IPC分类号： G11C11/14
CPC分类号： G11C19/0808 , G11C11/161 , G11C11/1673 , G11C11/1675
摘要： A magnetic track includes first and second magnetic domain regions having different lengths and different magnetic domain wall movement speeds. A longer of the first and second magnetic domain regions serves as an information read/write region. An information storage device includes a magnetic track. The magnetic track includes a plurality of magnetic domain regions and a magnetic domain wall region formed between neighboring magnetic domain regions. The plurality of magnetic domain regions includes a first magnetic domain region and at least one second magnetic domain region having a smaller length than the first magnetic domain region. The information storage device further includes a first unit configured to perform at least one of an information recording operation and an information reproducing operation on the first magnetic domain region, and a magnetic domain wall movement unit configured to move a magnetic domain wall of the magnetic domain wall region.
摘要翻译： 磁道包括具有不同长度和不同磁畴壁移动速度的第一和第二磁畴区域。 第一和第二磁畴区域中较长的区域用作信息读/写区域。 信息存储装置包括磁道。 磁道包括多个磁畴区域和形成在相邻磁畴区域之间的磁畴壁区域。 多个磁畴区域包括第一磁畴区域和具有比第一磁畴区域更小的长度的至少一个第二磁畴区域。 信息存储装置还包括被配置为在第一磁畴区域上执行信息记录操作和信息再现操作中的至少一个的第一单元和被配置为移动磁畴的磁畴壁的磁畴壁移动单元 墙区域。
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