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    Semiconductor Devices and Methods of Manufacture Thereof
    13.
    发明申请
    Semiconductor Devices and Methods of Manufacture Thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US20090039442A1

    公开(公告)日：2009-02-12

    申请号：US11834398

    申请日：2007-08-06

    Applicant: Jin-Ping Han ,  Thomas W. Dyer ,  Henry Utomo ,  Rajendran Krishnasamy

    Inventor： Jin-Ping Han ,  Thomas W. Dyer ,  Henry Utomo ,  Rajendran Krishnasamy

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762

    CPC classification number: H01L29/6656 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and forming at least one feature over the semiconductor wafer. A top portion of the at least one isolation structure is removed, and a liner is formed over the semiconductor wafer, the at least one feature, and the at least one isolation structure. A fill material is formed over the liner. The fill material and the liner are removed from over at least a portion of a top surface of the semiconductor wafer.

    Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供半导体晶片，在半导体晶片内形成至少一个隔离结构，并在半导体晶片上形成至少一个特征。 移除所述至少一个隔离结构的顶部，并且在所述半导体晶片，所述至少一个特征以及所述至少一个隔离结构之上形成衬垫。 在衬套上形成填充材料。 填充材料和衬垫从半导体晶片的顶表面的至少一部分上方被去除。

    Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions
    17.
    发明申请
    Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions 有权
    形成具有SiGe源极/漏极区域的P沟道场效应晶体管的方法

    公开(公告)号：US20110237039A1

    公开(公告)日：2011-09-29

    申请号：US12729486

    申请日：2010-03-23

    Applicant: Jong-Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    Inventor： Jong-Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

    IPC: H01L21/336

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

    Abstract: Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

    Abstract translation: 形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。 这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。 然后在栅极电极上形成掩模层。 选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。 然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。 在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。 然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

    Methods of Manufacturing Resistors and Structures Thereof
    19.
    发明申请
    Methods of Manufacturing Resistors and Structures Thereof 审中-公开
    制造电阻器及其结构的方法

    公开(公告)号：US20110175174A1

    公开(公告)日：2011-07-21

    申请号：US13077554

    申请日：2011-03-31

    Applicant: Knut Stahrenberg ,  Jin-Ping Han

    Inventor： Knut Stahrenberg ,  Jin-Ping Han

    IPC: H01L29/772

    CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L28/20

    Abstract: A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material.

    Abstract translation: 半导体器件包括第一半导体材料的半导体本体。 晶体管设置在半导体本体中。 晶体管包括嵌入半导体本体中的第二半导体材料的源区和漏区。 电阻器覆盖半导体主体的顶表面并与晶体管横向间隔开。 电阻器由第二半导体材料形成。

    Strained semiconductor device and method of making same
    20.
    发明授权
    Strained semiconductor device and method of making same 有权
    应变半导体器件及其制造方法

    公开(公告)号：US07772676B2

    公开(公告)日：2010-08-10

    申请号：US11473883

    申请日：2006-06-23

    Applicant: Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

    Inventor： Jin-Ping Han ,  Hung Y. Ng ,  Judson R. Holt

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor material. The compound semiconductor region has a concentration of the second semiconductor material that varies along an interface between the side portion of the compound semiconductor region and the side portion of the semiconductor body

    Abstract translation: 半导体本体由诸如硅的第一半导体材料形成。 诸如硅锗的化合物半导体区域被嵌入在半导体本体中。 化合物半导体区域包括第一半导体材料和第二半导体材料。 化合物半导体区域具有沿着化合物半导体区域的侧部与半导体本体的侧部之间的界面变化的第二半导体材料的浓度

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