摘要:
Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece, forming a gate dielectric material over the workpiece, the gate dielectric material comprising an insulator and at least one metal element, and forming a conductive material over the gate dielectric material. The conductive material comprises the at least one metal element of the gate dielectric material.
摘要:
A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.
摘要:
A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated in fabricating a CMOS structure containing silicide contacts and silicide gate metals.
摘要:
Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要:
A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.
摘要:
The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要:
A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode.
摘要:
Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.
摘要:
A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated with fabricating a CMOS structure containing silicide contacts and silicide gate metals.
摘要:
A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.