公开(公告)号：US08237141B2

公开(公告)日：2012-08-07

申请号：US12657345

申请日：2010-01-19

Applicant: Myung-jin Kang ,  Jun-soo Bae ,  Doo-hwan Park ,  Eun-hee Cho

Inventor： Myung-jin Kang ,  Jun-soo Bae ,  Doo-hwan Park ,  Eun-hee Cho

IPC: H01L45/00

CPC classification number: H01L45/141 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/144

Abstract: A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by InXSbYTeZ or, alternatively, with substitutions of silicon and/or tin for indium, arsenic and/or bismuth for antimony, and selenium for tellurium; and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer.

Abstract translation: 包括具有低工作电压和低功耗的相变材料的非易失性存储器件包括下电极; 相变材料层，形成在下电极上以与下电极电连接，其中相变材料层包括具有由InXSbYTeZ表示的组成的相变材料，或者替代地，硅和 /或锡用于铟，砷和/或锑的锑，硒用于碲; 以及形成在所述相变材料层上以与所述相变材料层电连接的上电极。

公开(公告)号：US07943918B2

公开(公告)日：2011-05-17

申请号：US12568402

申请日：2009-09-28

Applicant: Jeong-Hee Park ,  Ju-Chul Park ,  Jun-Soo Bae ,  Bong-Jin Kuh ,  Yong-Ho Ha

Inventor： Jeong-Hee Park ,  Ju-Chul Park ,  Jun-Soo Bae ,  Bong-Jin Kuh ,  Yong-Ho Ha

IPC: H01L45/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C2213/79 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

Abstract translation: 可变相存储器件包括相变材料图案，以及电连接到相变材料图案的第一和第二电极。 第一和第二电极被配置为向相变材料图案提供电信号。 相变材料图案包括第一相变材料层和第二相变材料层。 第一和第二可相变材料图案具有不同的化学，物理和/或电特性。 例如，第二可相变材料层的电阻率可以比第一相变材料层更大。 例如，第一相变材料层可以包括第一浓度的氮，第二相变材料层可以包括大于第一浓度的第二浓度的氮。 还讨论了相关设备和制造方法。

公开(公告)号：US20110026303A1

公开(公告)日：2011-02-03

申请号：US12901168

申请日：2010-10-08

Applicant: Byung-Gil Choi ,  Beak-hyung Cho ,  Jun Soo Bae ,  Kwang-Jin Lee

Inventor： Byung-Gil Choi ,  Beak-hyung Cho ,  Jun Soo Bae ,  Kwang-Jin Lee

IPC: G11C11/00

CPC classification number: G11C7/18 ,  G11C7/04 ,  G11C8/12 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2029/2602 ,  H01L27/24

Abstract: A nonvolatile memory device comprising: a plurality of memory banks, each of which operates independently and includes a plurality of resistance memory cells, each cell including a variable resistive element having a resistance varying depending on stored data; a plurality of global bit lines, each global bit line being shared by the plurality of memory banks; a temperature compensation circuit including one or more reference cells; and a data read circuit which is electrically connected to the plurality of global bit lines and performs a read operation by supplying at least one of the resistance memory cells with a current varying according to resistances of the reference cells.

Abstract translation: 一种非易失性存储器件，包括：多个存储体，每个存储体各自独立地操作并且包括多个电阻存储器单元，每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件; 多个全局位线，每个全局位线由多个存储体共享; 包括一个或多个参考单元的温度补偿电路; 以及数据读取电路，其电连接到所述多个全局位线，并且通过向所述电阻存储器单元中的至少一个提供根据所述参考单元的电阻而变化的电流来执行读取操作。

公开(公告)号：US07800095B2

公开(公告)日：2010-09-21

申请号：US11941173

申请日：2007-11-16

Applicant: Hyeong-geun An ,  Hideki Horii ,  Jong-chan Shin ,  Dong-ho Ahn ,  Jun-soo Bae

Inventor： Hyeong-geun An ,  Hideki Horii ,  Jong-chan Shin ,  Dong-ho Ahn ,  Jun-soo Bae

IPC: H01L47/00

CPC classification number: H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: Provided is a phase-change memory device including a phase-change material pattern of which strips are shared by neighboring cells. The phase-change memory device includes a plurality of bottom electrodes arranged in a matrix array. The phase-change material pattern is formed on the bottom electrodes, and the strips of the phase-change material pattern are electrically connected to the bottom electrodes. Each strip of the phase-change material pattern is connected to at least two diagonally neighboring bottom electrodes of the bottom electrodes.

Abstract translation: 提供了一种相变存储器件，其包括相邻单元共享条带的相变材料图案。 相变存储器件包括以矩阵阵列排列的多个底部电极。 相变材料图案形成在底部电极上，相变材料图案的条带电连接到底部电极。 相变材料图案的每个条带连接到底部电极的至少两个对角相邻的底部电极。

公开(公告)号：US20100213558A1

公开(公告)日：2010-08-26

申请号：US12773451

申请日：2010-05-04

Applicant: Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Kyung-Tae Nam

Inventor： Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Kyung-Tae Nam

IPC: H01L29/82

CPC classification number: G11C11/15 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3281 ,  H01F41/302 ,  H01L43/08

Abstract: A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

Abstract translation: 提供磁存储器件。 磁存储器件在衬底上包括不变的钉扎图案和可变的钉扎图案。 在不变的钉扎图案和可变钉扎图案之间插入隧道势垒图案，并且钉扎图案介于不变钉扎图案和隧道屏障图案之间。 在隧道势垒图案和可变钉扎图案之间插入无存储图案，并且在存储空闲图案和可变钉扎图案之间插入无引导图案。 在存储和无引导模式之间插入一个自由的反转模式。 自由反转图案反转无存储图案的磁化方向和反向自由图案的磁化方向。

公开(公告)号：US20100144087A1

公开(公告)日：2010-06-10

申请号：US12708742

申请日：2010-02-19

Applicant: Yong-Ho Ha ,  Bong-Jin Kuh ,  Ji-Hye Yi ,  Jun-Soo Bae

Inventor： Yong-Ho Ha ,  Bong-Jin Kuh ,  Ji-Hye Yi ,  Jun-Soo Bae

IPC: H01L21/8239

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.

Abstract translation: 相变存储器件包括电连接到衬底中的晶体管的杂质区的下电极和在下电极上包括第一相变材料的编程层图案。 包含具有比第一相变材料低的热导率的材料的绝热层图案在编程层图案上，上电极在绝热层图案上。

公开(公告)号：US20100103726A1

公开(公告)日：2010-04-29

申请号：US12652842

申请日：2010-01-06

Applicant: Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

Inventor： Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

IPC: G11C11/00 ,  G11C7/02 ,  G11C5/14

CPC classification number: G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

Abstract translation: 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US20090283741A1

公开(公告)日：2009-11-19

申请号：US12509048

申请日：2009-07-24

Applicant: Young-Soo Lim ,  Jun-Soo Bae

Inventor： Young-Soo Lim ,  Jun-Soo Bae

IPC: H01L47/00

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

Abstract: The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a phase changeable pattern. Oxygen plasma or water vapor plasma can then be provided to the upper electrode and the phase changeable pattern.

Abstract translation: 本发明涉及形成可变相结构的方法，其中上电极形成在相变层上。 可以向相变层和上电极提供包含氟的材料。 相变层可被蚀刻以形成相变图案。 然后可以将氧等离子体或水蒸气等离子体提供给上电极和相变图案。

公开(公告)号：US20090278107A1

公开(公告)日：2009-11-12

申请号：US12453334

申请日：2009-05-07

Applicant: Do-Hyung Kim ,  Jun-Soo Bae ,  Dong-Hyun Im ,  Sung-Lae Cho ,  Jin-II Lee ,  Hye-Young Park ,  Hee-Ju Shin

Inventor： Do-Hyung Kim ,  Jun-Soo Bae ,  Dong-Hyun Im ,  Sung-Lae Cho ,  Jin-II Lee ,  Hye-Young Park ,  Hee-Ju Shin

IPC: H01L47/00

CPC classification number: H01L45/143 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

Abstract: The phase change memory device includes a first electrode and a second electrode and a first phase change material pattern and a second phase change material pattern interposed between the first electrode and the second electrode, wherein the first and second phase change material patterns have respectively different electrical characteristics.

Abstract translation: 相变存储器件包括插入在第一电极和第二电极之间的第一电极和第二电极以及第一相变材料图案和第二相变材料图案，其中第一和第二相变材料图案分别具有不同的电 特点

公开(公告)号：US07558100B2

公开(公告)日：2009-07-07

申请号：US11881062

申请日：2007-07-25

Applicant: Dong-Ho Ahn ,  Hideki Horii ,  Jun-Soo Bae

Inventor： Dong-Ho Ahn ,  Hideki Horii ,  Jun-Soo Bae

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

Abstract: A phase change memory device may include an integrated circuit substrate and first and second phase change memory elements on the integrated circuit substrate. The first phase change memory element may include a first phase change material having a first crystallization temperature. The second phase change memory element may include a second phase change material having a second crystallization temperature. Moreover, the first and second crystallization temperatures may be different so that the first and second phase change memory elements are programmable at different temperatures. Related methods and systems are also discussed.

Abstract translation: 相变存储器件可以包括集成电路衬底以及集成电路衬底上的第一和第二相变存储元件。 第一相变存储元件可以包括具有第一结晶温度的第一相变材料。 第二相变存储元件可以包括具有第二结晶温度的第二相变材料。 此外，第一和第二结晶温度可以不同，使得第一和第二相变存储元件可在不同温度下编程。 还讨论了相关方法和系统。