中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

198 records (took 0.027 seconds)

    Input buffer for detecting an input signal
    11.
    发明授权
    Input buffer for detecting an input signal 失效
    用于检测输入信号的输入缓冲器

    公开(公告)号：US07948272B2

    公开(公告)日：2011-05-24

    申请号：US10990412

    申请日：2004-11-18

    Applicant: Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

    Inventor： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

    IPC: H03K5/22

    CPC classification number: H03K19/003

    Abstract: An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

    Abstract translation: 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。

    First delay locking method, delay-locked loop, and semiconductor memory device including the same
    12.
    发明授权
    First delay locking method, delay-locked loop, and semiconductor memory device including the same 失效
    第一延迟锁定方法，延迟锁定环和包括其的半导体存储器件

    公开(公告)号：US07936196B2

    公开(公告)日：2011-05-03

    申请号：US12716373

    申请日：2010-03-03

    Applicant: Jun Bae Kim ,  Chang-Hyun Bae ,  Jung-Bae Lee

    Inventor： Jun Bae Kim ,  Chang-Hyun Bae ,  Jung-Bae Lee

    IPC: H03L7/06

    CPC classification number: G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/091 ,  H03L7/10

    Abstract: According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.

    Abstract translation: 根据一个实施例，公开了一种在延迟锁定环电路中执行快速锁定的方法。 该方法包括执行将输入时钟信号与作为非反相反馈时钟信号的第一反馈时钟信号进行比较的第一比较，以及将输入时钟信号与作为反馈时钟信号的第二反馈时钟信号进行比较的第二比较 倒。 该方法还包括基于第一和第二比较，选择非反相反馈时钟信号或反相反馈时钟信号中的一个与输入时钟信号同步。 此外，该方法包括使所选择的时钟信号与输入时钟信号同步。

    CIRCUIT AND METHOD FOR GENERATING INTERNAL VOLTAGE, AND SEMICONDUCTOR DEVICE HAVING THE CIRCUIT
    13.
    发明申请
    CIRCUIT AND METHOD FOR GENERATING INTERNAL VOLTAGE, AND SEMICONDUCTOR DEVICE HAVING THE CIRCUIT 有权
    用于产生内部电压的电路和方法，以及具有电路的半导体器件

    公开(公告)号：US20110095814A1

    公开(公告)日：2011-04-28

    申请号：US12845279

    申请日：2010-07-28

    Applicant: So-Young Kim ,  Jung Sik Kim ,  Jang-Woo Ryu ,  Ho Cheol Lee ,  Jung Bae Lee

    Inventor： So-Young Kim ,  Jung Sik Kim ,  Jang-Woo Ryu ,  Ho Cheol Lee ,  Jung Bae Lee

    IPC: G05F1/10

    CPC classification number: G11C5/14

    Abstract: An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal.

    Abstract translation: 一种在半导体器件中执行的内部电压产生方法，所述内部电压产生方法包括产生对应于多个外部电源电压的多个初始化信号; 检测来自所述多个初始化信号中的最后生成的初始化信号的转变并产生检测信号; 以及根据检测信号产生第一内部电压。

    METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY
    14.
    发明申请
    METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY 有权
    在多端口半导体存储器中控制深度掉电模式的方法

    公开(公告)号：US20100309742A1

    公开(公告)日：2010-12-09

    申请号：US12768060

    申请日：2010-04-27

    Applicant: Ho-Cheol LEE ,  Jung-Bae LEE

    Inventor： Ho-Cheol LEE ,  Jung-Bae LEE

    IPC: G11C5/14 ,  G11C8/16

    CPC classification number: G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

    Abstract: Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

    Abstract translation: 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

    FIRST DELAY LOCKING METHOD, DELAY-LOCKED LOOP, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    16.
    发明申请
    FIRST DELAY LOCKING METHOD, DELAY-LOCKED LOOP, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 失效
    第一延迟锁定方法，延迟锁定环路和包括其的半导体存储器件

    公开(公告)号：US20100226188A1

    公开(公告)日：2010-09-09

    申请号：US12716373

    申请日：2010-03-03

    Applicant: Jun Bae Kim ,  Chang-Hyun Bae ,  Jung-Bae Lee

    Inventor： Jun Bae Kim ,  Chang-Hyun Bae ,  Jung-Bae Lee

    IPC: G11C7/00 ,  H03L7/06

    CPC classification number: G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/091 ,  H03L7/10

    Abstract: According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.

    Abstract translation: 根据一个实施例，公开了一种在延迟锁定环电路中执行快速锁定的方法。 该方法包括执行将输入时钟信号与作为非反相反馈时钟信号的第一反馈时钟信号进行比较的第一比较，以及将输入时钟信号与作为反馈时钟信号的第二反馈时钟信号进行比较的第二比较 倒。 该方法还包括基于第一和第二比较，选择非反相反馈时钟信号或反相反馈时钟信号之一以与输入时钟信号同步。 此外，该方法包括使所选择的时钟信号与输入时钟信号同步。

    Semiconductor memory device having shared temperature control circuit
    17.
    发明申请
    Semiconductor memory device having shared temperature control circuit 有权
    具有共享温度控制电路的半导体存储器件

    公开(公告)号：US20100157709A1

    公开(公告)日：2010-06-24

    申请号：US12589674

    申请日：2009-10-27

    Applicant: Ho-Young Kim ,  Jung-Bae Lee

    Inventor： Ho-Young Kim ,  Jung-Bae Lee

    IPC: G11C7/04 ,  G11C8/00 ,  G11C7/00

    CPC classification number: G11C29/02 ,  G11C5/143 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C29/028 ,  G11C2029/5002 ,  G11C2207/2254

    Abstract: A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding memory bank. The shared control circuit is connected to the plurality of temperature sensing circuits and a plurality of refresh circuits for refreshing the plurality of memory banks, performs calibration on the plurality of temperature sensing circuits, performs digital processing on signals for separately controlling refresh intervals for the plurality of memory banks, and transmits the processed signals to the plurality of refresh circuits. Therefore, the refresh intervals for individual channels or banks are separately or selectively controlled. Further, since the plurality of temperature sensing circuits are connected to the shared temperature control circuit, the occupied area of the circuits in a chip is reduced or minimized.

    Abstract translation: 半导体存储器件包括多个存储体; 多个温度检测电路和共享控制电路。 温度感测电路对应于存储体，并且各自设置在相应的存储体的附近。 共享控制电路连接到多个温度检测电路和多个刷新电路，用于刷新多个存储体，对多个温度感测电路进行校准，对用于分别控制多个温度感测电路的刷新间隔的信号执行数字处理 的存储体，并且将处理的信号发送到多个刷新电路。 因此，单独或选择性地控制各通道或组的刷新间隔。 此外，由于多个温度检测电路连接到共享温度控制电路，芯片中的电路的占用面积减小或最小化。

    Semiconductor memory device having variable-mode refresh operation
    18.
    发明申请
    Semiconductor memory device having variable-mode refresh operation 审中-公开
    具有可变模式刷新操作的半导体存储器件

    公开(公告)号：US20100124138A1

    公开(公告)日：2010-05-20

    申请号：US12585317

    申请日：2009-09-11

    Applicant: Dong-Hyuk Lee ,  Jung-Bae Lee

    Inventor： Dong-Hyuk Lee ,  Jung-Bae Lee

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C8/10 ,  G11C7/1075 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4013

    Abstract: A semiconductor memory device includes a bit line sense amplifier, a bit line pair that includes a bit line and a complementary bit line, the bit line and the complementary bit line of the bit line pair each being coupled to the bit line sense amplifier, a memory cell array having a plurality of memory banks, the memory banks including word lines and a plurality of memory cells, and a word line activation control unit that performs a control to access data corresponding to an externally same address in at least two memory cells by simultaneously activating a predetermined number of word lines from among the word lines sharing the bit line sense amplifier, and the word line activation control unit operates in response to a determination mode allowing signal that is set in accordance with a used memory density.

    Abstract translation: 半导体存储器件包括位线读出放大器，包括位线和互补位线的位线对，位线对的互补位线与位线读出放大器耦合， 具有多个存储体的存储单元阵列，所述存储体包括字线和多个存储器单元，以及字线激活控制单元，其执行控制以通过在至少两个存储器单元中访问对应于外部相同地址的数据进行控制 同时从共享位线读出放大器的字线中激活预定数量的字线，并且字线激活控制单元响应于根据所使用的存储器密度设置的确定模式允许信号来操作。

    Memory system and timing control method of the same
    20.
    发明授权
    Memory system and timing control method of the same 有权
    存储系统和时序控制方法相同

    公开(公告)号：US07447862B2

    公开(公告)日：2008-11-04

    申请号：US10886926

    申请日：2004-07-08

    Applicant: Jung-Bae Lee ,  Hoe-Ju Chung

    Inventor： Jung-Bae Lee ,  Hoe-Ju Chung

    IPC: G06F13/42

    CPC classification number: G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C2207/2254

    Abstract: A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.

    Abstract translation: 存储器系统包括至少一个存储器模块，每个存储器模块具有用于产生模式数据的模式数据产生电路，该模式数据具有共同应用命令信号的多个存储器，并且分别应用相应的数据; 以及存储器控制器，用于分别将命令信号和相应的数据应用于多个存储器，在定时控制操作期间向存储器模块应用模式数据产生命令，使用以下方式计算到达多个存储器中的每一个的数据之间的时间差： 从每个存储器输出的图案数据，并使用计算出的数据到达时间差来接收和输出数据。 因此，在存储器控制器和存储器之间实现稳定的数据传输。

Patent Agency Ranking