公开(公告)号：US10283698B2

公开(公告)日：2019-05-07

申请号：US15666903

申请日：2017-08-02

Applicant: Seung Pil Ko ,  Kiseok Suh ,  Kilho Lee ,  Daeeun Jeong

Inventor： Seung Pil Ko ,  Kiseok Suh ,  Kilho Lee ,  Daeeun Jeong

IPC: H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  H01L43/08 ,  H01L27/22 ,  H01L21/768 ,  H01L43/12 ,  H01L23/485 ,  H01L23/532

Abstract: A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.

公开(公告)号：US09691816B2

公开(公告)日：2017-06-27

申请号：US14964251

申请日：2015-12-09

Applicant: Shinhee Han ,  Kilho Lee ,  Yoonjong Song

Inventor： Shinhee Han ,  Kilho Lee ,  Yoonjong Song

IPC: H01L43/10 ,  H01L27/22 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.

公开(公告)号：US20170125666A1

公开(公告)日：2017-05-04

申请号：US15404325

申请日：2017-01-12

Applicant: Shinhee Han ,  Kilho Lee ,  Yoonjong Song

Inventor： Shinhee Han ,  Kilho Lee ,  Yoonjong Song

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.

公开(公告)号：US09576846B2

公开(公告)日：2017-02-21

申请号：US14226770

申请日：2014-03-26

Applicant: Kilho Lee

Inventor： Kilho Lee

IPC: H01L21/768 ,  H01L27/22

CPC classification number: H01L21/76816 ,  H01L27/228

Abstract: Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.

Abstract translation: 提供了用于制造数据存储装置的方法。 一种方法可以包括在衬底上形成层间电介质层，在衬底的周边区域中形成层间电介质层以形成第一沟槽，在第一沟槽中形成第一位线，将第一位线之间的层间介质层图形化 所述外围区域形成在形成所述第一位线之后沿着所述第一沟槽延伸的第二沟槽，以及在所述第二沟槽中形成第二位线。

公开(公告)号：US20150017742A1

公开(公告)日：2015-01-15

申请号：US14226770

申请日：2014-03-26

Applicant: KILHO LEE

Inventor： KILHO LEE

IPC: H01L21/768 ,  H01L27/22

CPC classification number: H01L21/76816 ,  H01L27/228

Abstract: Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.

Abstract translation: 提供了用于制造数据存储装置的方法。 一种方法可以包括在衬底上形成层间电介质层，在衬底的周边区域中形成层间电介质层以形成第一沟槽，在第一沟槽中形成第一位线，将第一位线之间的层间介质层图形化 所述外围区域形成在形成所述第一位线之后沿着所述第一沟槽延伸的第二沟槽，以及在所述第二沟槽中形成第二位线。

公开(公告)号：US06867087B2

公开(公告)日：2005-03-15

申请号：US09988183

申请日：2001-11-19

Applicant: Kilho Lee ,  Woo-Tang Kang ,  Rajesh Rengarajan

Inventor： Kilho Lee ,  Woo-Tang Kang ,  Rajesh Rengarajan

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising:a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site;b) forming an undoped polysilicon layer over the gate oxide layer;c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer;d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions;e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; andf) affecting cooling after laser annealing to convert a-Si into polysilicon without gate oxide damage.

Abstract translation: 在制造CMOS半导体结构的双功函数栅电极的方法中，改进包括形成双功函数栅电极，使得在沟道区中不渗透硼，在栅极氧化物附近没有硼耗尽，包括： a）在nMOS位点的沟道上和pMOS位点的沟道上形成栅极氧化层; b）在栅极氧化物层上形成未掺杂的多晶硅层; c）掩蔽pMOS位点，形成a-Si层 使用第一重离子注入的nMOS位点，并将砷单独注入到a-Si层中; d）掩蔽由步骤c）形成的nMOS位点，使用第二重离子注入在pMOS位点上形成a-Si层， 并且将硼单独注入到a-Si区域中; e）在短时间内和在足以熔化至少一部分a-Si但不足以熔化多晶硅的能级下激光退火nMOS和pMOS位点; 和f）影响激光退火后的冷却，将a-Si转换为多晶硅，而不会产生栅极氧化物损伤。

公开(公告)号：US06214661B1

公开(公告)日：2001-04-10

申请号：US09489771

申请日：2000-01-21

Applicant: Heon Lee ,  Young-Jin Park ,  Young Limb ,  Brian Lee ,  Kilho Lee ,  Satish Athavale ,  Jai-hoon Sim

Inventor： Heon Lee ,  Young-Jin Park ,  Young Limb ,  Brian Lee ,  Kilho Lee ,  Satish Athavale ,  Jai-hoon Sim

IPC: H01L218242

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L28/55

Abstract: In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: a) preparing a bottom Pt electrode formation; b) subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; c) depositing a BSTO layer on said oxygen enriched Pt layer; d) depositing an upper Pt electrode layer on the BSTO layer; e) subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and f) depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

Abstract translation: 在形成用于DRAM器件的Pt / BSTO / Pt电容器堆叠的微电子结构的方法中，改进包括基本上消除或防止BSTO材料层的氧扩散，包括：a）制备底部Pt电极 b）使底Pt层电极形成氧气等离子体处理，在底Pt电极上形成富氧Pt层; c）在所述富氧Pt层上沉积BSTO层; d）将上Pt电极层沉积在 BSTO层; e）使上Pt电极层进行氧等离子体处理以形成掺入氧的Pt层; 以及）在配有氧的Pt层上部Pt上沉积Pt层。

公开(公告)号：US10164170B2

公开(公告)日：2018-12-25

申请号：US15622064

申请日：2017-06-13

Applicant: Kiseok Suh ,  Byoungjae Bae ,  Gwanhyeob Koh ,  Yoonjong Song ,  Kilho Lee

Inventor： Kiseok Suh ,  Byoungjae Bae ,  Gwanhyeob Koh ,  Yoonjong Song ,  Kilho Lee

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22

Abstract: A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

公开(公告)号：US20160005739A1

公开(公告)日：2016-01-07

申请号：US14738814

申请日：2015-06-12

Applicant: KILHO LEE ,  SHINHEE HAN

Inventor： KILHO LEE ,  SHINHEE HAN

IPC: H01L27/105 ,  H01L23/528 ,  H01L21/28 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L29/423

CPC classification number: H01L21/76877 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/4236 ,  H01L29/66621 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion.

Abstract translation: 半导体存储器件包括覆盖基片的第一绝缘层，每个穿透第一绝缘层的第一接触插塞和第二接触插塞，设置在第一接触插塞上的第一数据存储元件和设置在第一绝缘层上的第二数据存储元件 第二个接触插头 第一接触插塞包括垂直延伸部分和布置在垂直延伸部分和第一数据存储元件之间的水平延伸部分，并且第二接触插塞从衬底的顶表面基本垂直地延伸。 当在平面图中观察时，第一数据存储元件与垂直延伸部分横向间隔开。 第一数据存储元件设置在水平延伸部分上。

公开(公告)号：US08872270B2

公开(公告)日：2014-10-28

申请号：US13686212

申请日：2012-11-27

Applicant: Kilho Lee ,  Ki Joon Kim ,  Se-Woong Park

Inventor： Kilho Lee ,  Ki Joon Kim ,  Se-Woong Park

IPC: H01L21/70 ,  H01L29/82 ,  H01L27/108

CPC classification number: H01L43/12 ,  H01L27/10888 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82

Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

Abstract translation: 存储器件及其制造方法包括：包括单元区域和外围电路区域的衬底，在单元区域上的数据存储，在数据存储器上并耦合到数据存储器的第一位线，耦合到外围电路区域上的外围晶体管的第一触点 以及在第一触点上并耦合到第一触点的第二位线。 第二位线可以各自具有低于数据存储器的最低表面的最下表面。