公开(公告)号：US5242840A

公开(公告)日：1993-09-07

申请号：US763293

申请日：1991-09-20

Applicant: Ki-Joon Kim

Inventor： Ki-Joon Kim

IPC: H01L27/15

CPC classification number: H01L27/153

Abstract: There is disclosed a method for making array capable of realizing large output and large-scale integration by using a heterogenous film which can electrically insulate between LEDs, (LEDs) by the diffusion of an impurity into a substrate. The improved LED array manufacturing method includes the steps of: forming a luminescent layer, of a first conductivity type, a transparent layer and a cap-layer over the semiconductor substrate, forming of a cap layer made into a given pattern by etching a given portion of said cap layer; forming of a diffusion region converted into the first conductivity type by the injection of an impurity into a given portion of the transparent layer; forming an oxide film on the entire surface except the area where the cap layer is covering the transparent layer 13; and forming an electrode over the cap layer and a common electrode under the semiconductor substrate.

Abstract translation: 公开了一种使阵列能够实现大输出和大规模集成的方法，该方法通过使用通过将杂质扩散到衬底中而使LED（LED）电绝缘的异质膜。 改进的LED阵列制造方法包括以下步骤：在半导体衬底上形成第一导电类型，透明层和盖层的发光层，通过蚀刻给定部分形成制成给定图案的盖层 的所述盖层; 通过将杂质注入到透明层的给定部分中，形成转变成第一导电类型的扩散区; 在覆盖透明层13的区域以外的整个表面上形成氧化膜; 以及在所述覆盖层上形成电极，在所述半导体衬底下方形成公共电极。

公开(公告)号：US5063420A

公开(公告)日：1991-11-05

申请号：US440673

申请日：1989-11-24

Applicant: Ki-Joon Kim

Inventor： Ki-Joon Kim

IPC: H01L27/15 ,  H01L33/08 ,  H01L33/14 ,  H01L33/30 ,  H01L33/40 ,  H01L33/44 ,  H05B33/00 ,  H05B33/10

CPC classification number: H01L27/153

Abstract: There is disclosed a method for making a light-emitting diode array capable of realizing large output and large-scale integration by using a heterogenous film which can electrically insulate between LEDs, (LEDs) by the diffusion of an impurity into a substrate. The improved LED array manufacturing method includes the steps of: forming a luminescent layer, of a first conductivity type, a transparent layer and a cap-layer over the semiconductor substrate; forming of a cap layer made into a given pattern by etching a given portion of said cap layer; forming of a diffusion region converted into the first conductivity type by the injection of an impurity into a given portion of the transparent layer; forming an oxide film on the entire surface except the area where the cap layer is covering the transparent layer; and forming an electrode over the cap layer and a common electrode under the semiconductor substrate.

Abstract translation: 公开了一种制造发光二极管阵列的方法，该发光二极管阵列能够通过使用通过将杂质扩散到衬底中而使LED（LED）电绝缘的异质膜来实现大输出和大规模集成。 改进的LED阵列制造方法包括以下步骤：在半导体衬底上形成第一导电类型，透明层和帽层的发光层; 通过蚀刻所述盖层的给定部分来形成制成给定图案的盖层; 通过将杂质注入到透明层的给定部分中，形成转变成第一导电类型的扩散区; 在覆盖透明层的区域以外的整个表面上形成氧化膜; 以及在所述覆盖层上形成电极，在所述半导体衬底下方形成公共电极。

公开(公告)号：US4999310A

公开(公告)日：1991-03-12

申请号：US399954

申请日：1989-08-29

Applicant: Ki-Joon Kim

Inventor： Ki-Joon Kim

IPC: B41J2/45 ,  H01L27/15 ,  H01L33/08 ,  H01L33/14 ,  H01L33/30

CPC classification number: H01L33/20 ,  B41J2/45 ,  H01L27/153 ,  H01L33/0062 ,  H01L33/305 ,  Y10S148/099

Abstract: A method of making an LED array capable of enhancing an internally generated light density with heterojunction by supporting the LED array with a current injection region by growing heterogeneous film and diffusing a zinc impurity. The improved LED array is capable of producing a high optical power by radiating efficiently a generated light beam without disturbance. To achieve the objects of the present invention, the method comprises: a first process for sequentially growing an n-type junction layer, a p-type radiative layer, a current blocking layer and n-type transparent layer over a semiconductor substrate; a second process for photo-etching the current blocking layer and n-type transparent layer in order to inject current; a third process for diffusing zinc impurity to form current injection region by electrically connecting p-type electrode with p-type radiative layer over the surface of current blocking layer as n-type transparent layer; a fourth process for performing a photo-etching so as to separate each element; and a fifth process for forming respective electrodes over the surface and inside of element.

Abstract translation: 一种制造LED阵列的方法，所述LED阵列能够通过产生非均相膜并扩散锌杂质，通过用电流注入区支持LED阵列，从而通过异质结增强内部产生的光密度。 改进的LED阵列能够通过有效地辐射产生的光束而无扰动地产生高光功率。 为了实现本发明的目的，该方法包括：在半导体衬底上顺序生长n型结层，p型辐射层，电流阻挡层和n型透明层的第一工艺; 用于光电蚀刻电流阻挡层和n型透明层以便注入电流的第二工艺; 通过将电流阻挡层的表面上的p型电极与p型辐射层电连接作为n型透明层，将锌杂质扩散形成电流注入区域的第三种工艺; 用于进行光蚀刻以分离每个元件的第四工艺; 以及在元件的表面和内部形成各个电极的第五工艺。

公开(公告)号：US20150140115A1

公开(公告)日：2015-05-21

申请号：US14547353

申请日：2014-11-19

Applicant: Ki Joon Kim

Inventor： Ki Joon Kim

IPC: A61K36/9068 ,  A61K36/28 ,  A61K36/752 ,  A61K36/8998 ,  A61K36/481 ,  A61K35/32 ,  A61K36/185 ,  A61K36/42 ,  A61K36/534 ,  A61K36/538 ,  A61K36/734 ,  A61K36/9064

CPC classification number: A61K36/9068 ,  A61K35/32 ,  A61K36/185 ,  A61K36/28 ,  A61K36/284 ,  A61K36/42 ,  A61K36/481 ,  A61K36/534 ,  A61K36/538 ,  A61K36/725 ,  A61K36/734 ,  A61K36/752 ,  A61K36/8998 ,  A61K36/9064 ,  A61K2236/00 ,  A61K2300/00

Abstract: The present invention relates to oriental medicine compositions marked as SEC 22 and SEC 33 for improving digestive functions and respiratory functions for improving children's underweight, low growth and depressed respiratory organ, an oriental medicine derived therefrom, and methods of preparing them. According to an example of the present invention, the oriental medicine composition containing broiled fruit of Crataegus pinnatifida, broiled root of Atractylodes japonica, dried peel of Citrus unshiu, broiled sprout of Hordeum vulgare, broiled fruit of Amomum xanthioides, root of Zingiber officinale, dried fruit of Zizyphi, and horn of Cervus elaphus.

Abstract translation: 本发明涉及标记为SEC22和SEC33的东方药物组合物，其用于改善消化功能和改善儿童体重不足，低生长和抑郁呼吸器官的呼吸功能，由其衍生的东方药及其制备方法。 根据本发明的一个实例，含有山楂烧烤水果的东方药物组合物，白术的炙根，柑橘干燥的干果，大麦的萌芽芽，野草根的苦果，干姜根 Zizyphi的果实和鹿茸的喇叭。

公开(公告)号：US20140264516A1

公开(公告)日：2014-09-18

申请号：US14210329

申请日：2014-03-13

Applicant: Bum-Seok SEO ,  Ki-Joon KIM ,  Kil-Ho LEE

Inventor： Bum-Seok SEO ,  Ki-Joon KIM ,  Kil-Ho LEE

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L27/228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

Abstract translation: 在基板上形成绝缘层。 在绝缘层上形成第一掩模。 第一掩模包括沿第二方向布置的多个线图案。 多个线图案沿着基本上垂直于第二方向的第一方向延伸。 在绝缘层和第一掩模上形成第二掩模。 第二掩模包括部分地暴露多个线图案的开口。 开口在第一方向的第一端部和第一方向的第三方向的第二方向的第一方向的一侧具有不均匀的边界。 使用第一掩模和第二掩模作为蚀刻掩模来部分去除绝缘层，从而形成多个第一沟槽和第二沟槽。 多个第一沟槽和第二沟槽以交错图案布置。

公开(公告)号：US20130040408A1

公开(公告)日：2013-02-14

申请号：US13569425

申请日：2012-08-08

Applicant: KyungTae Nam ,  Ki Joon Kim ,  Youngnam Hwang

Inventor： KyungTae Nam ,  Ki Joon Kim ,  Youngnam Hwang

IPC: H01L21/8239

CPC classification number: H01L21/76897 ,  H01L27/228 ,  H01L27/2436

Abstract: An exemplary method of forming a variable resistance memory may include forming first source/drain regions in a substrate, forming gate line structures and conductive isolation patterns buried in the substrate with the first source/drain regions interposed therebetween, and forming lower contact plugs on the first source/drain regions. The forming of lower contact plugs may include forming a first interlayer insulating layer, including a first recess region exposing the first source/drain regions adjacent to each other in a first direction, forming a conductive layer in the first recess region, patterning the conductive layer to form preliminary conductive patterns spaced apart from each other in the first direction, and patterning the preliminary conductive patterns to form conductive patterns spaced apart from each other in a second direction substantially orthogonal to the first direction.

Abstract translation: 形成可变电阻存储器的示例性方法可以包括在衬底中形成第一源极/漏极区域，形成栅极线结构和埋入衬底中的导电隔离图案，其中介于其间的第一源极/漏极区域形成下部接触插塞 第一源/漏区。 下接触塞的形成可以包括形成第一层间绝缘层，其包括在第一方向上暴露彼此相邻的第一源极/漏极区的第一凹部区域，在第一凹部区域中形成导电层，图案化导电层 以在第一方向上形成彼此间隔开的初步导电图案，并且将初步导电图案图案化以形成在与第一方向大致正交的第二方向上彼此间隔开的导电图案。

公开(公告)号：US20120099371A1

公开(公告)日：2012-04-26

申请号：US13343383

申请日：2012-01-04

Applicant: Cheol-kyu KIM ,  Yoon-ho Khang ,  Ki-joon Kim

Inventor： Cheol-kyu KIM ,  Yoon-ho Khang ,  Ki-joon Kim

IPC: G11C11/21

CPC classification number: G11C11/5678 ,  G11C13/0004

Abstract: A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied.

Abstract translation: 提供一种操作包括相变层和向相变层施加电压的单元的相变存储器件的方法。 该方法包括将复位电压施加到相变层，其中复位电压包括连续施加的至少两个脉冲电压。

公开(公告)号：US07994492B2

公开(公告)日：2011-08-09

申请号：US12232661

申请日：2008-09-22

Applicant: Youn-seon Kang ,  Ki-joon Kim ,  Cheol-kyu Kim ,  Tae-yon Lee

Inventor： Youn-seon Kang ,  Ki-joon Kim ,  Cheol-kyu Kim ,  Tae-yon Lee

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1625

Abstract: Disclosed may be a phase change material alloy, a phase change memory device including the same, and methods of manufacturing and operating the phase change memory device. The phase change material alloy may include Si and Sb. The alloy may be a Si—O—Sb alloy further including O. The Si—O—Sb alloy may be SixOySbz, wherein, when x/(x+z) may be x1, 0.05≦x1≦0.30, 0.00≦y≦0.50, and x+y+z may be 1. The Si—O—Sb alloy may further comprise an element other than Si, O, and Sb.

Abstract translation: 公开了相变材料合金，包括该相变材料合金的相变存储器，以及制造和操作相变存储器件的方法。 相变材料合金可以包括Si和Sb。 该合金可以是进一步包括O的Si-O-Sb合金.Si-O-Sb合金可以是SixOySbz，其中当x /（x + z）可以是x1,0.05＆nlE; x1＆nlE; 0.30,0.00＆ y和nl; 0.50和x + y + z可以为1.Si-O-Sb合金还可以包含除Si，O和Sb以外的元素。

公开(公告)号：US07763886B2

公开(公告)日：2010-07-27

申请号：US11980431

申请日：2007-10-31

Applicant: Yoon-ho Khang ,  Daniel Wamwangi ,  Matthias Wuttig ,  Ki-joon Kim ,  Dong-seok Suh

Inventor： Yoon-ho Khang ,  Daniel Wamwangi ,  Matthias Wuttig ,  Ki-joon Kim ,  Dong-seok Suh

IPC: H01L45/00 ,  C01B19/00

CPC classification number: C01B19/007 ,  C01P2002/52 ,  C01P2006/33 ,  C01P2006/34 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141

Abstract: Provided are a doped phase change material and a phase change memory device including the phase change material. The phase change material, which may be doped with Se, has a higher crystallization temperature than a Ge2Sb2Te5 (GST) material. The phase change material may be InXSbYTeZSe100−(X+Y+Z). The index X of indium (In) is in the range of 25 wt %≦X≦60 wt %. The index Y of antimony (Sb) is in the range of 1 wt %≦Y≦17 wt %. The index Z of tellurium (Te) is in the range of 0 wt %

Abstract translation: 提供了掺杂相变材料和包括相变材料的相变存储器件。 可以掺杂Se的相变材料具有比Ge2Sb2Te5（GST）材料更高的结晶温度。 相变材料可以是InXSbYTeZSe100-（X + Y + Z）。 铟（In）的指数X在25重量％＆lt; lE; X＆lt; lE; 60重量％的范围内。 锑（Sb）的指数Y在1重量％＆lt; 1E; Y＆lt; 1; 17重量％的范围内。 碲（Te）的指数Z在0重量％

公开(公告)号：US20090283738A1

公开(公告)日：2009-11-19

申请号：US12213234

申请日：2008-06-17

Applicant: Tae-yon Lee ,  Ki-Joon Kim ,  Jun-ho Lee ,  Cheol-Kyu Kim

Inventor： Tae-yon Lee ,  Ki-Joon Kim ,  Jun-ho Lee ,  Cheol-Kyu Kim

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/148

Abstract: Provided is a phase-change memory using a single-element semimetallic thin film. The device includes a storage node having a phase-change material layer and a switching element connected to the storage node, wherein the storage node includes a single-element semimetallic thin film which is formed between an upper electrode and a lower electrode. Thus, the write speed of the phase-change memory can be increased compared with the case of a Ge—Sb—Te (GST) based material.

Abstract translation: 提供了使用单元件半金属薄膜的相变存储器。 该装置包括具有相变材料层和连接到存储节点的开关元件的存储节点，其中存储节点包括形成在上电极和下电极之间的单元件半金属薄膜。 因此，与基于Ge-Sb-Te（GST）的材料的情况相比，可以提高相变存储器的写入速度。