公开(公告)号：US20090283738A1

公开(公告)日：2009-11-19

申请号：US12213234

申请日：2008-06-17

Applicant: Tae-yon Lee ,  Ki-Joon Kim ,  Jun-ho Lee ,  Cheol-Kyu Kim

Inventor： Tae-yon Lee ,  Ki-Joon Kim ,  Jun-ho Lee ,  Cheol-Kyu Kim

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/148

Abstract: Provided is a phase-change memory using a single-element semimetallic thin film. The device includes a storage node having a phase-change material layer and a switching element connected to the storage node, wherein the storage node includes a single-element semimetallic thin film which is formed between an upper electrode and a lower electrode. Thus, the write speed of the phase-change memory can be increased compared with the case of a Ge—Sb—Te (GST) based material.

Abstract translation: 提供了使用单元件半金属薄膜的相变存储器。 该装置包括具有相变材料层和连接到存储节点的开关元件的存储节点，其中存储节点包括形成在上电极和下电极之间的单元件半金属薄膜。 因此，与基于Ge-Sb-Te（GST）的材料的情况相比，可以提高相变存储器的写入速度。

公开(公告)号：US20080093591A1

公开(公告)日：2008-04-24

申请号：US11907844

申请日：2007-10-18

Applicant: Yoon-ho Khang ,  Ki-Joon Kim ,  Dong-seok Suh

Inventor： Yoon-ho Khang ,  Ki-Joon Kim ,  Dong-seok Suh

IPC: H01L47/00 ,  H01L21/06

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

Abstract: A storage node may include a bottom electrode contact layer, a phase change layer connected to the bottom electrode contact layer, and a top electrode layer connected to the phase change layer. The bottom electrode contact layer may protrude toward the phase change layer. A phase change memory device may include a switching device and the storage node. The switching device may be connected to the bottom electrode contact layer. A method of manufacturing the storage node may include forming a via hole in an insulating interlayer, at least partially filling the via hole to form a bottom electrode contact layer, protruding the bottom electrode contact layer from the via hole, and forming a phase change layer that covers the bottom electrode contact layer. A method of manufacturing a phase change memory device may include forming the switching device on a substrate and manufacturing the storage node.

Abstract translation: 存储节点可以包括底部电极接触层，连接到底部电极接触层的相变层和连接到相变层的顶部电极层。 底部电极接触层可以向相变层突出。 相变存储器件可以包括切换装置和存储节点。 开关器件可以连接到底部电极接触层。 制造存储节点的方法可以包括在绝缘中间层中形成通孔，至少部分地填充通孔以形成底电极接触层，从底孔电极接触层从通孔突出，并形成相变层 覆盖底部电极接触层。 相变存储器件的制造方法可以包括在基板上形成开关器件并制造存储节点。

公开(公告)号：US20070184613A1

公开(公告)日：2007-08-09

申请号：US11703126

申请日：2007-02-07

Applicant: Ki-Joon Kim ,  Yoon-Ho Khang ,  Jin-Seo Noh

Inventor： Ki-Joon Kim ,  Yoon-Ho Khang ,  Jin-Seo Noh

IPC: H01L21/336

CPC classification number: H01L29/8615 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/73 ,  H01L29/24 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A phase change RAM (PRAM) including a resistance element having a diode function, and methods of fabricating and operating the same are provided. The PRAM may include a substrate, a phase change diode layer formed on the substrate and an upper electrode formed on the phase change diode layer. The phase change diode layer may include a material layer doped with first impurities, and a phase change layer which is stacked on the doped layer. The phase change layer may show characteristics of a semiconductor material doped with impurities having an opposite conductive type to that of the first impurities.

Abstract translation: 提供了包括具有二极管功能的电阻元件的相变RAM（PRAM）及其制造和操作方法。 PRAM可以包括衬底，形成在衬底上的相变二极管层和形成在相变二极管层上的上电极。 相变二极管层可以包括掺杂有第一杂质的材料层和层叠在掺杂层上的相变层。 相变层可以显示掺杂有与第一杂质导电类型相反的导电类型的杂质的半导体材料的特性。

公开(公告)号：US6147385A

公开(公告)日：2000-11-14

申请号：US218819

申请日：1998-12-22

Applicant: Sung-Bong Kim ,  Ki-Joon Kim ,  Jong-Mil Youn

Inventor： Sung-Bong Kim ,  Ki-Joon Kim ,  Jong-Mil Youn

IPC: H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L27/11 ,  H01L27/1104 ,  Y10S257/903

Abstract: A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions. The drain region of the second load transistor is disposed between the drain region of the first load transistor and the second common region. First and second gate electrode layers are disposed generally parallel to each other, and respectively serving as the gates of the first driving transistor and the first load transistor and as the gates of the second driving transistor and the second load transistor, wherein each of the first and second gate electrode layers is made of a conductive material of a first level. First and second interconnecting layers are each made of a conductive material of a second level different from the first level, the first interconnecting layer connecting the first common region to the drain region of the first load transistor and the second gate electrode layer, the second interconnecting layer connecting the second common region to the drain region of the second load transistor and the first gate electrode layer.

Abstract translation: 描述具有减小的纵横比的能力的完整CMOS SRAM单元。 SRAM单元包括n沟道类型的第一和第二传输晶体管，n沟道类型的第一和第二驱动晶体管以及p沟道类型的第一和第二负载晶体管。 每个晶体管在形成在半导体衬底中的沟道区的相对侧上具有源极和漏极区域，并且在沟道区域上具有栅极。 单元包括由第一传输晶体管的漏极区域和串联连接的第一驱动晶体管限定的第一公共区域。 第二公共区域由第二传输晶体管和串联连接的第二驱动晶体管的漏极区限定。 第一负载晶体管的漏极区域设置成与第一和第二公共区域之间的第一公共区域相邻。 第二负载晶体管的漏极区域设置在第一负载晶体管的漏极区域和第二公共区域之间。 第一和第二栅极电极层大体上彼此平行地设置，并且分别用作第一驱动晶体管和第一负载晶体管的栅极，以及作为第二驱动晶体管和第二负载晶体管的栅极，其中第一 并且第二栅电极层由第一级的导电材料制成。 第一和第二互连层各自由不同于第一电平的第二电平的导电材料制成，第一互连层将第一公共区域连接到第一负载晶体管的漏极区域和第二栅极电极层，第二互连 将第二公共区域连接到第二负载晶体管的漏极区域和第一栅极电极层的层。

公开(公告)号：US09379003B2

公开(公告)日：2016-06-28

申请号：US14053932

申请日：2013-10-15

Applicant: Kil-Ho Lee ,  Se-Woong Park ,  Ki-Joon Kim

Inventor： Kil-Ho Lee ,  Se-Woong Park ,  Ki-Joon Kim

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/7681 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

Abstract translation: 公开了一种半导体器件和形成半导体器件的方法。 在该方法中，在衬底上形成诸如绝缘中间层的层。 在该层中形成第一沟槽，并且在第一沟槽中形成掩模层。 掩模层具有从第一沟槽的底表面到掩模层的顶部的第一厚度。 图案化掩模层以形成至少部分地暴露第一沟槽的侧壁的掩模。 与第一沟槽的暴露的侧壁相邻的掩模的一部分具有小于第一厚度的第二厚度。 使用掩模作为蚀刻掩模蚀刻该层以形成第二沟槽。 第二沟槽与第一沟槽流体连通。 在第一沟槽和第二沟槽中形成导电图案。

公开(公告)号：US07592993B2

公开(公告)日：2009-09-22

申请号：US11255834

申请日：2005-10-21

Applicant: Ki-Joon Kim

Inventor： Ki-Joon Kim

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0291 ,  G09G2310/08

Abstract: There is provided a source driver capable of controlling the timing of source line driving signals in a liquid crystal display device. The source driver includes a plurality of output circuits, each output circuit including an output buffer and a switch. The output buffer amplifies an analog image signal, and the switch outputs the amplified analog image signal as a source line driving signal in response to a control signal. The source driver further comprises a control circuit for generating the control signal, the control circuit comprising: a delay circuit delaying a switch signal and generating a delayed switch signal; and a multiplexer selecting one of the switch signal and the delayed switch signal in response to a selection signal and outputting the selected signal as the control signal.

Abstract translation: 提供了能够控制液晶显示装置中的源极线驱动信号的定时的源极驱动器。 源极驱动器包括多个输出电路，每个输出电路包括输出缓冲器和开关。 输出缓冲器放大模拟图像信号，并且开关响应于控制信号而输出放大的模拟图像信号作为源极线驱动信号。 源极驱动器还包括用于产生控制信号的控制电路，所述控制电路包括：延迟电路，延迟开关信号并产生延迟的开关信号; 以及多路复用器，响应于选择信号选择开关信号和延迟开关信号之一，并输出所选择的信号作为控制信号。

公开(公告)号：US20090184727A1

公开(公告)日：2009-07-23

申请号：US12223967

申请日：2007-02-13

Applicant: Ki-Joon Kim ,  Yong-Hwi Jo ,  Dong Yeul Choi

Inventor： Ki-Joon Kim ,  Yong-Hwi Jo ,  Dong Yeul Choi

IPC: G01R31/02 ,  H05K3/10

CPC classification number: G01R1/07378 ,  G01R31/2889 ,  Y10T29/49155

Abstract: Provided is a probe card of a semiconductor testing apparatus, including a printed circuit board to which an electrical signal is applied from external, a space transformer having a plurality of probes directly contacting with a test object, and interconnectors connecting the printed circuit board to the probes of the space transformer. The space transformer includes substrate pieces which the probes are installed on one sides of, and a combination member joining and unifying the substrate pieces together so as to form a large-area substrate with the substrate pieces on the same plane. This probe card is advantageous to improving flatness even with a large area, as well as testing semiconductor chips formed on a wafer in a lump.

Abstract translation: 提供一种半导体测试装置的探针卡，包括从外部施加电信号的印刷电路板，具有与测试对象直接接触的多个探针的空间变压器以及将印刷电路板连接到测试对象的互连器 空间变压器探头。 空间变压器包括探针安装在其一侧的基片和将基片拼接在一起的组合件，以便形成具有基片的同一平面上的大面积基片。 该探针卡有利于即使在大面积上提高平坦度，也有利于测试在一个晶片上形成的半导体芯片。

公开(公告)号：US20090128180A1

公开(公告)日：2009-05-21

申请号：US11990275

申请日：2006-08-02

Applicant: Ki-Joon Kim ,  Yong-Hwi Jo

Inventor： Ki-Joon Kim ,  Yong-Hwi Jo

IPC: G01R1/067 ,  G01R31/02 ,  C25F3/12

CPC classification number: G01R1/06727 ,  G01R3/00 ,  Y10T29/49004

Abstract: Disclosed is a cantilever-type probe and methods of fabricating the same. The probe is comprised of a cantilever being longer lengthwise relative to the directions of width and height, and a tip extending from the bottom of the cantilever and formed at an end of the cantilever. A section of the tip parallel to the bottom of the cantilever is rectangular, having four sides slant to the lengthwise direction of the cantilever.

Abstract translation: 公开了一种悬臂式探针及其制造方法。 探头由相对于宽度和高度方向的纵向长度的悬臂组成，以及从悬臂的底部延伸并形成在悬臂的端部处的尖端。 平行于悬臂底部的尖端的一部分是矩形的，具有沿着悬臂的长度方向倾斜的四个边。

公开(公告)号：US4918029A

公开(公告)日：1990-04-17

申请号：US157981

申请日：1988-02-19

Applicant: Ki-Joon Kim

Inventor： Ki-Joon Kim

IPC: H01L21/208 ,  C30B19/02 ,  C30B19/06 ,  C30B19/08

CPC classification number: C30B19/02 ,  C30B19/063 ,  C30B19/08 ,  C30B29/40 ,  Y10S148/101

Abstract: A device and method for liquid-phase thin film epitaxial growth are disclosed wherein yield and quality of semiconductors in the fabrication sequences are improved. The device comprises an electric furnace which is disposed outside a quartz tube, a plurality of boats which are disposed within the quartz tube in accordance with a sort of melting liquids and a plurality of auxiliary heating devices are disposed around the boats with a power source independent from the electric furnace. According to this fabrication sequence, after heating the inner part of the quartz tube up to a first temperature level by supplying the power source to the electric furnace, the melting liquids are firstly melted down enough by means of selectively heating the auxiliary heating devices up to a second temperature level higher than the first temperature level, the substrates are then moved to be in contact with the melting liquids and an epitaxial growth layer is consequently formed through selectively reducing the temperature of the auxiliary heating devices to other levels different from the first and second level.

Abstract translation: 公开了用于液相薄膜外延生长的装置和方法，其中制造顺序中的半导体的产率和质量得到改善。 该装置包括设置在石英管外部的电炉，根据一种熔化液体和多个辅助加热装置设置在石英管内的多个船只设置在船舶周围，电源独立 从电炉。 根据该制造顺序，通过向电炉供给电源，将石英管的内部部分加热到第一温度水平之后，熔融液首先通过选择性地加热辅助加热装置而熔化到最高 第二温度水平高于第一温度水平，然后基板移动以与熔化液体接触，因此通过选择性地将辅助加热装置的温度降低到与第一和第二温度不同的其他水平，形成外延生长层 二级

公开(公告)号：US09118002B2

公开(公告)日：2015-08-25

申请号：US14210329

申请日：2014-03-13

Applicant: Bum-Seok Seo ,  Ki-Joon Kim ,  Kil-Ho Lee

Inventor： Bum-Seok Seo ,  Ki-Joon Kim ,  Kil-Ho Lee

IPC: H01L43/02 ,  H01L43/12 ,  H01L21/311 ,  H01L29/82 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L27/228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

Abstract translation: 在基板上形成绝缘层。 在绝缘层上形成第一掩模。 第一掩模包括沿第二方向布置的多个线图案。 多个线图案沿着基本上垂直于第二方向的第一方向延伸。 在绝缘层和第一掩模上形成第二掩模。 第二掩模包括部分地暴露多个线图案的开口。 开口在第一方向的第一端部和第一方向的第三方向的第二方向的第一方向的一侧具有不均匀的边界。 使用第一掩模和第二掩模作为蚀刻掩模来部分去除绝缘层，从而形成多个第一沟槽和第二沟槽。 多个第一沟槽和第二沟槽以交错图案布置。