公开(公告)号：US20080122520A1

公开(公告)日：2008-05-29

申请号：US11424132

申请日：2006-06-14

Applicant: Kiyoshi Kase ,  Dzung T. Tran ,  May Len

Inventor： Kiyoshi Kase ,  Dzung T. Tran ,  May Len

IPC: G05F3/02

CPC classification number: G05F3/205

Abstract: In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

Abstract translation: 在一种形式中，电路具有偏置级，其具有用于接收输入信号的输入信号端子。 该电路用驱动级修改输入信号以提供补码形式的输出信号。 电路的驱动级中的驱动晶体管具有连接到负载的端子和耦合到输入信号端子的控制电极的体积。 电路的偏置级中的偏置晶体管具有直接连接到负载的端子和驱动晶体管体的体积。 偏置晶体管具有耦合到输入信号端子的控制电极。 输入信号偏置驱动晶体管和偏置晶体管的体积，并降低晶体管阈值电压。 电路输出阻抗的线性提高，RF干扰降低。 还提供较低的电压操作。

公开(公告)号：US20080116952A1

公开(公告)日：2008-05-22

申请号：US11561209

申请日：2006-11-17

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03K3/01

CPC classification number: H03K3/3565

Abstract: An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

Abstract translation: 具有迟滞的输入缓冲电路包括第一级和第二级。 第一级包括用于在第一级的两个节点之间提供电阻的电阻装置。 两个节点响应信号输入。 第二级包括四个串联耦合晶体管。 第一节点耦合到四个晶体管中的两个的控制电极，并且第二节点耦合到另外两个晶体管的控制电极。 第二级包括信号输出。 在一些示例中，由电阻装置提供的电阻是可变的并且为缓冲电路提供迟滞。

公开(公告)号：US07268524B2

公开(公告)日：2007-09-11

申请号：US10891811

申请日：2004-07-15

Applicant: Kiyoshi Kase ,  May Len

Inventor： Kiyoshi Kase ,  May Len

IPC: G05F1/40

CPC classification number: G05F1/575

Abstract: A voltage regulator includes a first and second amplifier stage, an output stage, and a variable zero circuit. The first amplifier stage is coupled to receive a reference voltage and introduces a first pole of the voltage regulator. The second amplifier stage is coupled to the first amplifier stage and introduces a second pole of the voltage regulator. The output stage is coupled to the second amplifier stage, has an output driver, and is coupled to provide an output voltage based on the reference voltage. The variable zero circuit is coupled to the first amplifier stage, the second amplifier stage, and the output stage. The variable zero circuit provides a zero to compensate for at least one of the first pole or the second pole of the voltage regulator based on a gate to source voltage of the output driver and a drain to source voltage of the output driver.

Abstract translation: 电压调节器包括第一和第二放大器级，输出级和可变零电路。 第一放大器级耦合以接收参考电压并引入电压调节器的第一极。 第二放大器级耦合到第一放大器级并引入电压调节器的第二极。 输出级耦合到第二放大器级，具有输出驱动器，并且被耦合以提供基于参考电压的输出电压。 可变零电路耦合到第一放大器级，第二放大级和输出级。 基于输出驱动器的栅极 - 源极电压和输出驱动器的漏极 - 源极电压，可变零电路提供零以补偿电压调节器的第一极点或第二极点中的至少一个极点。

公开(公告)号：US07109782B2

公开(公告)日：2006-09-19

申请号：US10958831

申请日：2004-10-05

Applicant: Kiyoshi Kase

Inventor： Kiyoshi Kase

IPC: G05F1/10

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A well bias module outputs a voltage used to bias the wells of transistors or other semiconductor components. The well bias module includes a feedback loop having a voltage generation module and a subthreshold leakage sense module that is operable to model the transistors or other semiconductor components so as to sense the subthreshold leakage resulting from a particular well bias voltage output by the voltage generation module. The subthreshold leakage sense module provides a representation of the sensed subthreshold leakage to the voltage generation module, which adjusts the magnitude of the well bias voltage based on this representation so as to reduce or minimize the subthreshold leakage in the transistors or other semiconductor components.

公开(公告)号：US07002371B2

公开(公告)日：2006-02-21

申请号：US10747748

申请日：2003-12-29

Applicant: Kiyoshi Kase ,  May Len ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  May Len ,  Dzung T. Tran

IPC: H03K19/094

CPC classification number: H03K17/102 ,  H03K3/356008 ,  H03K3/356113

Abstract: A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.

Abstract translation: 具有不同阈值电压的交叉耦合反相器的电平移位器。 在上电期间，电平转换器的输出被拉到已知的电压状态。 在一些示例中，一个反相器包括附加的N沟道晶体管，其中由于附加晶体管，阈值电压大于另一个反相器的阈值电压。

公开(公告)号：US6137429A

公开(公告)日：2000-10-24

申请号：US265238

申请日：1999-03-08

Applicant: Joseph Y. Chan ,  David Yatim ,  Kiyoshi Kase ,  Paul Astrachan

Inventor： Joseph Y. Chan ,  David Yatim ,  Kiyoshi Kase ,  Paul Astrachan

IPC: H03M1/08 ,  H03M3/02 ,  H03M3/00

CPC classification number: H03M3/324 ,  H03M3/37 ,  H03M3/50

Abstract: A data converter (10) and a method for attenuating noise in an output signal generated by the data converter (10). The data converter (10) includes a sigma-delta modulator (16), a digital-to-analog converter (17), a clock generator (19) connected to the digital-to-analog converter (17), and a clock control circuit (18) connected to the clock generator (19). The clock control circuit (18) enables or disables the clock generator (19) in accordance with the single-bit digital signal to cause a notch characteristic in the output signal for attenuating noise in the output signal.

Abstract translation: 数据转换器（10）和用于衰减由数据转换器（10）产生的输出信号中的噪声的方法。 数据转换器（10）包括Σ-Δ调制器（16），数模转换器（17），连接到数模转换器（17）的时钟发生器（19）和时钟控制 电路（18）连接到时钟发生器（19）。 时钟控制电路（18）根据单比特数字信号启用或禁用时钟发生器（19），以使得输出信号中的陷波特性衰减输出信号中的噪声。

公开(公告)号：US5124704A

公开(公告)日：1992-06-23

申请号：US583130

申请日：1990-09-17

Applicant: Kiyoshi Kase ,  Hisashi Sekiguchi

Inventor： Kiyoshi Kase ,  Hisashi Sekiguchi

IPC: H03M1/10 ,  H03M1/36

CPC classification number: H03M1/108 ,  H03M1/36

Abstract: Apparatus and procedure for testing a flash analog-to-digital converter on a chip including a first NOR gate having a plurality of inputs, one each connected to each normal output of the comparators and a second NOR gate having a plurality of inputs, one each connected to each inverted output of the comparators. The output currents of the NOR gates are monitored to determine the states of the comparators when various input voltages are supplied. All comparators are tested for operation.

公开(公告)号：US4922493A

公开(公告)日：1990-05-01

申请号：US232191

申请日：1988-08-15

Applicant: Kiyoshi Kase

Inventor： Kiyoshi Kase

IPC: G06F11/18 ,  G06K7/00 ,  H03K5/1252 ,  H04L25/06

CPC classification number: H04L25/068 ,  G06K7/0008 ,  G06K7/0013 ,  G06K7/0086 ,  H03K5/1252

Abstract: An overload circuit detects input signals that are too high or too low in amplitude and generates a holding signal of a predetermined duration. The holding signal is applied to a data selector which normally passes the input signal to a shift register/majority gate but switches to supply the output of the majority gate to the shift register when a holding signal is present. Thus, the output is maintained constant during the predetermined durations when a holding singnal is present.

公开(公告)号：US08923465B2

公开(公告)日：2014-12-30

申请号：US12988831

申请日：2008-05-19

Applicant: Conor O'Keeffe ,  Kiyoshi Kase ,  Paul Kelleher

Inventor： Conor O'Keeffe ,  Kiyoshi Kase ,  Paul Kelleher

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0337

Abstract: A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.

Abstract translation: 半导体器件包括采样逻辑，包括：输入采样路径选择逻辑，布置成使能至少一个输入采样路径; 采样器逻辑，被布置为根据所述至少一个使能的输入采样路径的相位接收和采样串行数据流中的输入数据信号; 以及转移检测逻辑，被布置成检测所接收的输入数据信号内的转变。 在检测到所接收的输入数据信号中的转换之后，进一步布置输入采样路径选择逻辑，以确定至少一个输入采样路径的相位是否是在逻辑值之间具有最大窗口的相位; 并且如果确定所述至少一个输入采样路径的相位不是在逻辑值之间具有最大窗口的相位，以使得能够进行包括更适当相位的至少一个输入采样路径。

公开(公告)号：US20110043253A1

公开(公告)日：2011-02-24

申请号：US12988831

申请日：2008-05-19

Applicant: Conor O'Keeffe ,  Kiyoshi Kase ,  Paul Kelleher

Inventor： Conor O'Keeffe ,  Kiyoshi Kase ,  Paul Kelleher

IPC: H03D13/00

CPC classification number: H04L7/0337

Abstract: A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.

Abstract translation: 半导体器件包括采样逻辑，包括：输入采样路径选择逻辑，布置成使能至少一个输入采样路径; 采样器逻辑，被布置为根据所述至少一个使能的输入采样路径的相位接收和采样串行数据流中的输入数据信号; 以及转移检测逻辑，被布置成检测所接收的输入数据信号内的转变。 在检测到所接收的输入数据信号中的转换之后，进一步布置输入采样路径选择逻辑，以确定至少一个输入采样路径的相位是否是在逻辑值之间具有最大窗口的相位; 并且如果确定所述至少一个输入采样路径的相位不是在逻辑值之间具有最大窗口的相位，以使得能够进行包括更适当相位的至少一个输入采样路径。