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    Digital to analog converter with reduced ringing
    14.
    发明授权
    Digital to analog converter with reduced ringing 有权
    数模转换器减少振铃

    公开(公告)号：US06714150B2

    公开(公告)日：2004-03-30

    申请号：US10320016

    申请日：2002-12-16

    Applicant: Klaas Bult ,  Chi-Hung Lin

    Inventor： Klaas Bult ,  Chi-Hung Lin

    IPC: H03M166

    CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

    Abstract translation: 二进制指示被转换为模拟表示，在连续的二进制指示之间的转换和每个二进制指示期间的周期中显着地减少振铃。 二进制指示以行和列矩阵布置以提供温度计代码。 转换器的每个级包括一个解码器和锁存器，所述解码器和锁存器被布置成使得解码器输入在锁存器被时钟脉冲设置之前稳定。 这些阶段在互补CMOS中实现。 互补晶体管是偏置的，因此该对的一个晶体管被驱动到轨道，而另一个晶体管则浮动。 虚拟CMOS晶体管用于平衡解码器路径中的晶体管数量。

    Analog to digital converter
    16.
    发明授权
    Analog to digital converter 有权
    模数转换器

    公开(公告)号：US6100836A

    公开(公告)日：2000-08-08

    申请号：US189096

    申请日：1998-11-09

    Applicant: Klaas Bult

    Inventor： Klaas Bult

    IPC: H03M1/06 ,  H03M1/36

    CPC classification number: H03M1/0646 ,  H03M1/36

    Abstract: An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells. Current sources connected to the output terminals of the transistors in the first and second branches have characteristics (preferably impedances approaching infinity) to force the load bearing currents from the transistors to flow through the impedances in the first and second sets. The impedances have relatively low values, particularly in comparison to the impedances of the current sources, to reduce cell mismatches. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop to minimize averaging errors at the ends of the strip.

    Abstract translation: 从多个单元形成在集成电路芯片上的模数转换器（ADC）包括具有第一和第二分支的差分放大器。 每个单元中的分支分别具有第一和第二晶体管，其分别响应于参考电压的输入电压和逐行分数的单独一个。 每个单元的分支的相对输出取决于引入单元的两个电压的相对值。 为了最小化单元错配和这些不匹配对单元输出的影响，第一和第二组平均阻抗（优选电阻器）分别连接在第一分支晶体管的输出端之间以及第二分支晶体管的输出端之间， 连续的细胞对。 连接到第一和第二分支中的晶体管的输出端子的电流源具有强制来自晶体管的负载电流流过第一和第二组中的阻抗的特性（优选地是接近无穷大的阻抗）。 阻抗具有相对较低的值，特别是与电流源的阻抗相比，减少电池不匹配。 芯片上的第一和第二电阻条可以在逐行位置被分接，以分别限定第一和第二组中的阻抗。 每个条带的一端可以连接到另一条带的相对端，以限定闭合阻抗环路，以最小化条带端部处的平均误差。

    High-efficiency class-AB amplifier
    18.
    发明申请
    High-efficiency class-AB amplifier 有权
    高效率AB类放大器

    公开(公告)号：US20070273442A1

    公开(公告)日：2007-11-29

    申请号：US11798293

    申请日：2007-05-11

    Applicant: Ovidiu Bajdechi ,  Christopher M. Ward ,  Klaas Bult

    Inventor： Ovidiu Bajdechi ,  Christopher M. Ward ,  Klaas Bult

    IPC: H03F3/45

    CPC classification number: H03F3/3028 ,  H03F1/0261 ,  H03F3/45192 ,  H03F3/45219 ,  H03F2203/30033 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45244 ,  H03F2203/45302 ,  H03F2203/45641 ,  H03F2203/45732

    Abstract: A high efficiency class-AB amplifier is disclosed. The amplifier comprises a first input stage and a second input stage, both coupled to a class-AB biasing mesh and an output stage, wherein the outputs of the first and second input stages are directly coupled to the output transistors in the output stage. In one embodiment, a first gate of the first input stage and of the second input stage are coupled together to receive the same input and a second gate of the first input stage and of the second input stage are coupled together to receive the same input. In another embodiment, the first input stage and second input stage may further comprise cascode transistors for coupling the two input stages to the class-AB biasing mesh. In yet another embodiment, a 3V supply is used and 1V transistors are used to improve gain and 3V transistors are used to protect the 1V transistors.

    Abstract translation: 公开了一种高效率AB类放大器。 放大器包括耦合到AB类偏置网格和输出级的第一输入级和第二输入级，其中第一和第二输入级的输出直接耦合到输出级中的输出晶体管。 在一个实施例中，第一输入级和第二输入级的第一栅极耦合在一起以接收相同的输入，并且第一输入级和第二输入级的第二栅极耦合在一起以接收相同的输入。 在另一个实施例中，第一输入级和第二输入级还可以包括用于将两个输入级耦合到AB类偏置网的共源共栅晶体管。 在另一个实施例中，使用3V电源，并且使用1V晶体管来改善增益，并且使用3V晶体管来保护1V晶体管。

    Method for operating an analog to digital converter
    20.
    发明授权
    Method for operating an analog to digital converter 失效
    用于操作模数转换器的方法

    公开(公告)号：US07170435B2

    公开(公告)日：2007-01-30

    申请号：US10810053

    申请日：2004-03-26

    Applicant: Klaas Bult ,  Chi-Hung Lin

    Inventor： Klaas Bult ,  Chi-Hung Lin

    IPC: H03M1/66

    CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

    Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

    Abstract translation: 二进制指示被转换为模拟表示，在连续的二进制指示之间的转换和每个二进制指示期间的周期中显着地减少振铃。 二进制指示以行和列矩阵布置以提供温度计代码。 转换器的每个级包括一个解码器和锁存器，所述解码器和锁存器布置成使得解码器输入在锁存器被时钟脉冲设置之前稳定。 这些阶段在互补CMOS中实现。 互补晶体管是偏置的，因此该对的一个晶体管被驱动到轨道，而另一个晶体管则浮动。 虚拟CMOS晶体管用于平衡解码器路径中的晶体管数量。

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