公开(公告)号：US07671681B2

公开(公告)日：2010-03-02

申请号：US10282688

申请日：2002-10-29

Applicant: Arya R. Behzad ,  Klaas Bult ,  Ramon A. Gomez ,  Chi-Hung Lin ,  Tom W. Kwan ,  Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

Inventor： Arya R. Behzad ,  Klaas Bult ,  Ramon A. Gomez ,  Chi-Hung Lin ,  Tom W. Kwan ,  Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC: H03G3/10

CPC classification number: H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

Abstract translation: 电路从集成电路可编程增益衰减器中的信号路径中去除开关。 可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。 这种开关可能在信号中引入非线性。 通过将开关与信号路径隔离，可以提高PGA的线性度。

公开(公告)号：US20070273442A1

公开(公告)日：2007-11-29

申请号：US11798293

申请日：2007-05-11

Applicant: Ovidiu Bajdechi ,  Christopher M. Ward ,  Klaas Bult

Inventor： Ovidiu Bajdechi ,  Christopher M. Ward ,  Klaas Bult

IPC: H03F3/45

CPC classification number: H03F3/3028 ,  H03F1/0261 ,  H03F3/45192 ,  H03F3/45219 ,  H03F2203/30033 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45244 ,  H03F2203/45302 ,  H03F2203/45641 ,  H03F2203/45732

Abstract: A high efficiency class-AB amplifier is disclosed. The amplifier comprises a first input stage and a second input stage, both coupled to a class-AB biasing mesh and an output stage, wherein the outputs of the first and second input stages are directly coupled to the output transistors in the output stage. In one embodiment, a first gate of the first input stage and of the second input stage are coupled together to receive the same input and a second gate of the first input stage and of the second input stage are coupled together to receive the same input. In another embodiment, the first input stage and second input stage may further comprise cascode transistors for coupling the two input stages to the class-AB biasing mesh. In yet another embodiment, a 3V supply is used and 1V transistors are used to improve gain and 3V transistors are used to protect the 1V transistors.

Abstract translation: 公开了一种高效率AB类放大器。 放大器包括耦合到AB类偏置网格和输出级的第一输入级和第二输入级，其中第一和第二输入级的输出直接耦合到输出级中的输出晶体管。 在一个实施例中，第一输入级和第二输入级的第一栅极耦合在一起以接收相同的输入，并且第一输入级和第二输入级的第二栅极耦合在一起以接收相同的输入。 在另一个实施例中，第一输入级和第二输入级还可以包括用于将两个输入级耦合到AB类偏置网的共源共栅晶体管。 在另一个实施例中，使用3V电源，并且使用1V晶体管来改善增益，并且使用3V晶体管来保护1V晶体管。

公开(公告)号：US20070120605A1

公开(公告)日：2007-05-31

申请号：US11698162

申请日：2007-01-26

Applicant: Klaas Bult ,  Ramon Gomez

Inventor： Klaas Bult ,  Ramon Gomez

IPC: H03G3/00

CPC classification number: H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

公开(公告)号：US07170435B2

公开(公告)日：2007-01-30

申请号：US10810053

申请日：2004-03-26

Applicant: Klaas Bult ,  Chi-Hung Lin

Inventor： Klaas Bult ,  Chi-Hung Lin

IPC: H03M1/66

CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract translation: 二进制指示被转换为模拟表示，在连续的二进制指示之间的转换和每个二进制指示期间的周期中显着地减少振铃。 二进制指示以行和列矩阵布置以提供温度计代码。 转换器的每个级包括一个解码器和锁存器，所述解码器和锁存器布置成使得解码器输入在锁存器被时钟脉冲设置之前稳定。 这些阶段在互补CMOS中实现。 互补晶体管是偏置的，因此该对的一个晶体管被驱动到轨道，而另一个晶体管则浮动。 虚拟CMOS晶体管用于平衡解码器路径中的晶体管数量。

公开(公告)号：US20060229046A1

公开(公告)日：2006-10-12

申请号：US11432435

申请日：2006-05-12

Applicant: Klaas Bult ,  Rudy Plassche ,  Arnoldus Venes

Inventor： Klaas Bult ,  Rudy Plassche ,  Arnoldus Venes

IPC: H04B1/06 ,  H04B7/00

CPC classification number: H03G3/30 ,  H03F1/34 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45188 ,  H03F3/45192 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/372 ,  H03F2200/513 ,  H03F2203/45644 ,  H03G1/0029 ,  H04B2001/0433

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

公开(公告)号：US20060192614A1

公开(公告)日：2006-08-31

申请号：US11345946

申请日：2006-02-02

Applicant: Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

Inventor： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC: H03B1/00

CPC classification number: H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

公开(公告)号：US07092043B2

公开(公告)日：2006-08-15

申请号：US09439101

申请日：1999-11-12

Applicant: Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr ,  Christopher M. Ward ,  Ralph Duncan ,  Tom W. Kwan ,  James Y. C. Chang ,  Haideh Khorramabadi

Inventor： Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr ,  Christopher M. Ward ,  Ralph Duncan ,  Tom W. Kwan ,  James Y. C. Chang ,  Haideh Khorramabadi

IPC: H04N5/455

CPC classification number: H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Abstract translation: 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。

公开(公告)号：US06650267B2

公开(公告)日：2003-11-18

申请号：US10146259

申请日：2002-05-15

Applicant: Klaas Bult ,  Aaron W. Buchwald

Inventor： Klaas Bult ,  Aaron W. Buchwald

IPC: H03M112

CPC classification number: H03M1/0646 ,  H03M1/36

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets.

公开(公告)号：US06573851B2

公开(公告)日：2003-06-03

申请号：US10079814

申请日：2002-02-22

Applicant: Klaas Bult

Inventor： Klaas Bult

IPC: H03M112

CPC classification number: H03F3/70 ,  H03M1/361

Abstract: A system and method for converting an analog input signal to a N-bit digital output signal. The invention comprises generating a plurality of reference voltage signals; pre-amplifying, separately, a difference between each of the plurality of reference voltage signals and an analog input signal using a plurality of cascaded, differential, switched-capacitor circuits to output a plurality of pre-amplified difference signals; and determining a zero-crossing result for each of the plurality of pre-amplified difference signals. Then one of a binary 1 and a binary 0 are assigned to each of the compared, pre-amplified signals. The binary 1's and 0's are encoded as an M-bit encoded signal, which is then decoded to output an N-bit digital output signal, wherein M is less that or equal to N.

Abstract translation: 一种用于将模拟输入信号转换成N位数字输出信号的系统和方法。 本发明包括产生多个参考电压信号; 分别对多个参考电压信号中的每一个和使用多个级联差分开关电容电路的模拟输入信号进行预放大，以输出多个预放大的差分信号; 以及确定所述多个预放大差分信号中的每一个的过零结果。 然后将二进制1和二进制0中的一个分配给每个比较的预放大信号。 二进制1和0被编码为M位编码信号，然后将其解码以输出N位数字输出信号，其中M小于或等于N.

公开(公告)号：US06522279B2

公开(公告)日：2003-02-18

申请号：US10175663

申请日：2002-06-20

Applicant: Klaas Bult ,  Chi-Hung Lin

Inventor： Klaas Bult ,  Chi-Hung Lin

IPC: H03M166

CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.