公开(公告)号：US07961026B2

公开(公告)日：2011-06-14

申请号：US12003676

申请日：2007-12-31

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03H11/26

CPC classification number: H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

Abstract translation: 通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。 延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。 锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器 响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

公开(公告)号：US07906985B2

公开(公告)日：2011-03-15

申请号：US12494433

申请日：2009-06-30

Applicant: Kyung-Hoon Kim ,  Sang-Sic Yoon

Inventor： Kyung-Hoon Kim ,  Sang-Sic Yoon

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K17/164 ,  H03K17/167

Abstract: A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal.

Abstract translation: 半导体器件包括多个数据驱动单元，每个数据驱动单元被配置为响应于相应的数据驱动单元，通过由电源电压输入引脚提供的电源电压和通过接地电压输入引脚提供的接地电压来驱动对应的数据输出焊盘 数据代码的位;模式感测单元，被配置为感测数据代码的位模式并生成模式感测信号;以及幻影驱动单元，被配置为在电源电压输入引脚和接地电压输入之间形成电流路径 并且通过响应于图案感测信号确定的驱动力来驱动电流路径。

公开(公告)号：US07884647B2

公开(公告)日：2011-02-08

申请号：US12326990

申请日：2008-12-03

Applicant: Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: H03K19/0175

CPC classification number: H03K19/018528

Abstract: There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.

Abstract translation: 提供了一种输出驱动器，其包括配置为响应于数据信号产生主驱动控制信号的预驱动器，配置成响应于主驱动控制信号驱动输出端的主驱动器，辅助驱动控制 信号发生器，其被配置为产生具有与数据信号和间隔控制信号对应的激活间隔的辅助驱动控制信号，以及配置为响应于辅助驱动控制信号来驱动输出端子的辅助驱动器。

公开(公告)号：US07816962B2

公开(公告)日：2010-10-19

申请号：US12284060

申请日：2008-09-18

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03L7/06

CPC classification number: G11C7/222 ,  G11C7/22 ,  H03L7/0814 ,  H03L7/085

Abstract: A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The delay locked loop includes a pattern detecting unit for generating and storing a noise pattern by detecting inputted noise data, a pre-delay control unit for determining a delay amount depending on the output of the pattern detecting unit, and a pre-delay line for delaying an internal clock depending on the delay amount that is determined by the pre-delay control means.

Abstract translation: 延迟锁定环可以消除由于常规DLL中的反馈等待时间而不可避免地发生的抖动分量。 也就是说，本发明通过基于预测数据控制延迟线来消除抖动分量的益处。 延迟锁定环包括：图案检测单元，用于通过检测输入的噪声数据产生和存储噪声模式;预延迟控制单元，用于根据模式检测单元的输出确定延迟量;以及预延迟线， 根据由预延迟控制装置确定的延迟量来延迟内部时钟。

公开(公告)号：US20100091598A1

公开(公告)日：2010-04-15

申请号：US12345835

申请日：2008-12-30

Applicant: Kyung Hoon KIM ,  Sang Sic YOON ,  Hong Bae KIM

Inventor： Kyung Hoon KIM ,  Sang Sic YOON ,  Hong Bae KIM

IPC: G11C8/06 ,  G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048

Abstract: A semiconductor memory apparatus includes a first data selection section inputted with the first data and second data and output one of the first data and the second data as first selection data in response to an address signal, a second data selection section inputted with the second data and the first selection data and output one of the second data and the first selection data as second selection data depending upon an input and output mode, and a data output section configured to be inputted with the first and second selection data and output first and second output data.

Abstract translation: 半导体存储装置包括：第一数据选择部，输入第一数据和第二数据，并响应于地址信号输出第一数据和第二数据之一作为第一选择数据;第二数据选择部，输入第二数据 和第一选择数据，并且根据输入和输出模式将第二数据和第一选择数据中的一个作为第二选择数据输出，以及数据输出部分，被配置为输入第一和第二选择数据并输出第一和第二 输出数据。

公开(公告)号：US07668028B2

公开(公告)日：2010-02-23

申请号：US11819812

申请日：2007-06-29

Applicant: Kyung-Hoon Kim ,  Yong-Ki Kim

Inventor： Kyung-Hoon Kim ,  Yong-Ki Kim

IPC: G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC classification number: G11C29/48 ,  G11C5/04 ,  G11C29/1201 ,  G11C2029/5602

Abstract: A dual in-line memory module (DIMM) for use in test includes a memory array with a plurality of memories, a test signal input/output unit, and a normal data input/output unit. The test signal input/output unit is provided in the respective memories to perform an input/output operation of a test signal with an external test mode controller for a test mode operation. The normal data input/output unit is provided in the respective memories to perform an input/output operation of a normal data with an external memory controller for a normal mode operation.

Abstract translation: 用于测试的双列直插存储器模块（DIMM）包括具有多个存储器的存储器阵列，测试信号输入/输出单元和正常数据输入/输出单元。 测试信号输入/输出单元设置在各个存储器中，以便通过用于测试模式操作的外部测试模式控制器执行测试信号的输入/输出操作。 正常数据输入/输出单元设置在相应的存储器中，以用于正常模式操作的外部存储器控制器执行正常数据的输入/输出操作。

公开(公告)号：US20090325548A1

公开(公告)日：2009-12-31

申请号：US12365191

申请日：2009-02-04

Applicant: Kyung-hoon KIM

Inventor： Kyung-hoon KIM

IPC: H04M3/42

CPC classification number: H04L67/2804 ,  H04L67/04 ,  H04L67/2814

Abstract: A method and an apparatus for providing an output service by using a mobile communication device through a network are provided. The method of providing a network output service, includes: receiving network identification address information of reproduction service information selected by a mobile communication device, based on an output request of the mobile communication device; requesting to provide output information corresponding to reproduction service information based on the network identification address information of the reproduction service information; receiving output information including the reproduction service information and additional service information; and providing output service information including a combination of the reproduction service information and the additional service information, based on the output information.

Abstract translation: 提供了一种通过网络使用移动通信设备来提供输出服务的方法和装置。 提供网络输出服务的方法包括：基于移动通信设备的输出请求，接收由移动通信设备选择的再现服务信息的网络标识地址信息; 基于所述再现服务信息的网络识别地址信息，请求提供与再现服务信息相对应的输出信息; 接收包括再现服务信息和附加服务信息的输出信息; 以及基于输出信息提供包括再现服务信息和附加服务信息的组合的输出服务信息。

公开(公告)号：US20090307851A1

公开(公告)日：2009-12-17

申请号：US12466495

申请日：2009-05-15

Applicant: Sun Cheol Bae ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

Inventor： Sun Cheol Bae ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

IPC: D06F33/00

CPC classification number: D06F35/006

Abstract: A washing machine and a method of controlling a washing machine are provided. The washing machine may include a drum in which laundry is provided and is rotated. The drum may operate at a first speed such that part of the laundry tumbles within the drum and another part of the laundry adheres to the drum. An unbalance amount or a first speed operation time of the drum, which is detected when the drum operates at the first speed, may be determined. When an abnormality occurs, rotation of the drum may stop or decelerate. Accordingly, at the time of a dehydration cycle, stability of the washing machine and laundry balancing can be ensured.

Abstract translation: 提供洗衣机和洗衣机的控制方法。 洗衣机可以包括其中设置有衣物并旋转的滚筒。 滚筒可以以第一速度操作，使得衣物的一部分在滚筒内滚动，另一部分衣物粘附在滚筒上。 可以确定当滚筒以第一速度操作时检测到的滚筒的不平衡量或第一速度操作时间。 发生异常时，滚筒的转动可能停止或减速。 因此，在脱水循环时，可以确保洗衣机的稳定性和衣物平衡。

公开(公告)号：US20090300851A1

公开(公告)日：2009-12-10

申请号：US12470800

申请日：2009-05-22

Applicant: Sun Cheol BAE ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

Inventor： Sun Cheol BAE ,  Kyung Hoon Kim ,  Han Su Jung ,  Jae Hyeok Choi ,  Ja In Koo

IPC: D06F33/00 ,  D06F39/00

CPC classification number: D06F35/007 ,  D06F37/203

Abstract: The present invention relates to a washing machine and a method of controlling the washing machine. According to the washing machine and the method of controlling the washing machine in accordance with the present invention, the drum is operated at a first speed so that part of laundry tumbles within the drum and another part of the laundry adheres to the drum. When a unbalance amount of the drum operating at the first speed is a first specific value or less, increasing the speed of the drum to a second speed so that the laundry adheres to the drum. When a unbalance amount of the drum detected during increasing to the second speed is a second specific value or more, decelerating the rotation of the drum. Accordingly, at the time of a dehydration cycle, stability of the washing machine and laundry balancing can be ensured.

Abstract translation: 洗衣机及洗衣机的控制方法技术领域本发明涉及洗衣机及洗衣机的控制方法。 根据本发明的洗衣机和洗衣机的控制方法，以第一速度操作滚筒，使得滚筒内部的衣物滚动部分和衣物的另一部分粘附在滚筒上。 当以第一速度操作的鼓的不平衡量是第一特定值或更小时，将滚筒的速度提高到第二速度，使得衣物粘附到滚筒。 当在增加到第二速度期间检测到的滚筒的不平衡量是第二特定值或更大时，减速滚筒的旋转。 因此，在脱水循环时，可以确保洗衣机的稳定性和衣物平衡。

公开(公告)号：US20090273493A1

公开(公告)日：2009-11-05

申请号：US12215772

申请日：2008-06-30

Applicant: Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

Inventor： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

IPC: H03M9/00

CPC classification number: H03M9/00

Abstract: A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

Abstract translation: 并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出 数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。