公开(公告)号：US11355187B2

公开(公告)日：2022-06-07

申请号：US17140064

申请日：2021-01-02

Applicant: Microchip Technology Inc.

Inventor： Victor Nguyen ,  Fethi Dhaoui ,  John L McCollum ,  Fengliang Xue

IPC: G11C13/00 ,  H01L45/00

Abstract: A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.

公开(公告)号：US11313702B2

公开(公告)日：2022-04-26

申请号：US17075157

申请日：2020-10-20

Applicant: Microchip Technology Inc.

Inventor： Stephane Le Goff ,  Mathieu Sureau ,  Jebas Paul Daniel T ,  Naveen Cannankurichi ,  Subhasis Sasmal ,  Sunny Joel

IPC: G01D5/24 ,  G01D5/244 ,  G01D5/20 ,  G01B7/00

Abstract: A system and method for monitoring analog front-end (AFE) circuitry of an inductive position sensor. A redundant AFE channel is provided and alternatively utilized with a sine AFE channel or a cosine AFE channel of the AFE circuitry to obtain a voltage difference that may result in a detection angle error at the electronic control unit (ECU) of the inductive position sensor.

公开(公告)号：US20220115282A1

公开(公告)日：2022-04-14

申请号：US17556790

申请日：2021-12-20

Applicant: Microchip Technology Inc.

Inventor： Matthias Klein ,  Andreas Zakrzewski ,  Richard Gruenwald

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A method for forming a packaged electronic die includes forming a plurality of bonding pads on a device wafer. A photoresist layer is deposited over the device wafer and is patterned so as to form a photoresist frame that completely surrounds a device formed on the device wafer. Conductive balls are deposited over the bonding pads. The wafer is cut to form the electronic die and the electronic die is placed over the substrate. The conductive balls are heated and compressed, moving the electronic die closer to the substrate such that the photoresist frame is in direct contact with the substrate or with a landing pad formed on the substrate. Encapsulant material is deposited such that the encapsulant material covers the electronic die and the substrate. The encapsulant material is cured so as to encapsulate the electronic die. The substrate is cut to separate the packaged electronic die.

公开(公告)号：US20220093397A1

公开(公告)日：2022-03-24

申请号：US17542303

申请日：2021-12-03

Applicant: Microchip Technology Inc.

Inventor： Amaury Gendron-Hansen ,  Bruce Odekirk

IPC: H01L21/02 ,  H01L21/04 ,  H01L27/092 ,  H01L21/67

Abstract: A silicon carbide semiconductor device includes a silicon carbide (SiC) substrate having a SiC epitaxial layer disposed over a surface of the SiC substrate, the SiC substrate having a first conductivity and the SiC epitaxial layer having the first conductivity. A contact region and a well region are formed in the SiC epitaxial layer, the contact region and the well region have a doping level of a second conductivity opposite the first conductivity. The contact region lies completely within the well region, is not in contact with a region having the first conductivity and has edges recessed from edges of the well region.

公开(公告)号：US20210374086A1

公开(公告)日：2021-12-02

申请号：US17151316

申请日：2021-01-18

Applicant: Microchip Technology Inc.

Inventor： Derin Jose ,  Sachindranath Pv ,  Viswas G

IPC: G06F13/42 ,  G06F13/362 ,  G06F13/10 ,  G06F13/40 ,  G06F9/50 ,  G06F9/48

Abstract: System and method for sharing a PCIe endpoint device with a plurality of host computers, by allocating a quantum of time to a host computer of a plurality of host computers coupled to a PCIe switch, wherein the quantum of time identifies a duration of time during which the host computer has exclusive access to a shareable PCIe endpoint device coupled to the PCIe switch. Requests from the host computer are transmitted to an emulated PCIe endpoint device of the PCIe switch during the quantum of time and the requests are then redirected from the emulated PCIe endpoint device to the shareable PCIe endpoint device during the quantum of time allocated to the host computer.

公开(公告)号：US20210359604A1

公开(公告)日：2021-11-18

申请号：US17244882

申请日：2021-04-29

Applicant: Microchip Technology Inc.

Inventor： Jason Rabb

IPC: H02M3/158 ,  H04Q1/28

Abstract: A system and method for generating a low supply voltage and a high supply voltage from an input voltage, wherein the dependency of the high supply voltage magnitude on the magnitude of the input voltage is removed and the resulting high supply voltage magnitude is a multiple of the low supply voltage magnitude. The low supply voltage and the high voltage may be implemented in a power converter of a communication system comprising a plurality of subscriber line interface circuits (SLICs).

公开(公告)号：US11158703B2

公开(公告)日：2021-10-26

申请号：US16446557

申请日：2019-06-19

Applicant: Microchip Technology Inc.

Inventor： Amaury Gendron-Hansen ,  Dumitru Sdrulla

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L21/761 ,  H01L29/16 ,  H01L29/78

Abstract: A high-voltage termination for a semiconductor device includes a substrate of a first conductivity type, an implanted device region of a second conductivity type of the semiconductor device, a shallow trench disposed in the substrate adjacent to the implanted device region, a doped extension region of the second conductivity type extending between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region, a junction termination extension region of the second conductivity type formed in the shallow trench contacting the extension region and extending past a second edge of the shallow trench opposite the implanted device region, an insulating layer formed over at least a portion of the extension region and over the junction termination extension region, and a metal layer formed over the insulating layer extending into at least a portion of the shallow trench and electrically connected to the extension region.

公开(公告)号：US11108895B2

公开(公告)日：2021-08-31

申请号：US16562994

申请日：2019-09-06

Applicant: Microchip Technology Inc.

Inventor： Winston Mok ,  Steven Scott Gorshe

IPC: H04L12/26 ,  H04L29/06 ,  H04L29/08

Abstract: A method for extracting path overhead (POH) data blocks from a data stream in a 64B/66B-block communication link, the method includes receiving at a sink node a data stream in a 64B/66B-block communication link, detecting within the data stream at a PCS sublayer a micro-packet starting with an /S/ control block, including K POH data blocks, and ending with a /T/ control block, extracting the micro-packet from the data stream, and extracting the POH data blocks from the micro-packet.

公开(公告)号：US11086716B2

公开(公告)日：2021-08-10

申请号：US16790547

申请日：2020-02-13

Applicant: Microchip Technology Inc.

Inventor： Peter John Waldemar Graumann

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/41 ,  H03M13/43 ,  H03M13/01 ,  H03M13/25

Abstract: A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.

公开(公告)号：US20210210402A1

公开(公告)日：2021-07-08

申请号：US16816874

申请日：2020-03-12

Applicant: Microchip Technology Inc.

Inventor： Damian McCann

IPC: H01L23/367 ,  H01L23/373

Abstract: A thermal management package for a semiconductor device includes a high dielectric constant material substrate, a high thermal conductivity slug disposed in a first window in the high dielectric constant material substrate and held therein by a first bonding material, an outer substrate formed from a material having a low dielectric constant and having a second window formed therein, the high dielectric constant material substrate disposed in the second window in the low dielectric constant outer substrate and held therein by a second bonding material.