公开(公告)号：US12260895B2

公开(公告)日：2025-03-25

申请号：US17464671

申请日：2021-09-01

Applicant: Micron Technology, Inc.

Inventor： Bryce D. Cook

IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4091 ,  G11C29/38

Abstract: Methods, apparatuses and systems related to protecting an apparatus against unauthorized accesses or usages are described. The apparatus may include a data protection circuit that protects an operating state of the apparatus, data stored in the apparatus, or a combination thereof when a temperature of the apparatus is outside of an operating range thereof.

公开(公告)号：US12260471B2

公开(公告)日：2025-03-25

申请号：US17887674

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Bhumika Chhabra ,  Radhika Viswanathan ,  Carla L. Christensen ,  Zahra Hosseinimakarem

IPC: G06T11/00 ,  G01C21/36 ,  G06Q10/08 ,  G06Q30/018 ,  G06Q30/0601

Abstract: Methods and devices systems related to a computing device for highlighting a tagged object with augmented reality (AR) are described. An example method can include identifying, using a computing device, an object tagged with a sensor within a plurality of objects. The example method can include tracking movement of the object based on communication between the sensor and the computing device and highlighting the object via AR based on the tracking and responsive to a request to locate the object.

公开(公告)号：US12260313B2

公开(公告)日：2025-03-25

申请号：US16951768

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Saideep Tiku ,  Poorna Kale

IPC: G06N3/045 ,  G06N3/08

Abstract: Apparatuses and methods can be related to implementing bypass paths in an ANN. The bypass path can be used to bypass a portion of the ANN such that the ANN generates an output with a particular level of confidence while utilizing less resources than if the portion of the ANN had not been bypassed.

公开(公告)号：US20250096042A1

公开(公告)日：2025-03-20

申请号：US18970741

申请日：2024-12-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20250095746A1

公开(公告)日：2025-03-20

申请号：US18967011

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Carmine Miccoli ,  Andrew Bicksler

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to program the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of one or more programming pulses satisfies a condition. The first set voltage is adjusted to a second step voltage level in response to the condition being satisfied.

公开(公告)号：US20250095718A1

公开(公告)日：2025-03-20

申请号：US18788001

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Christopher Morzano

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094

Abstract: Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

公开(公告)号：US20250095713A1

公开(公告)日：2025-03-20

申请号：US18958966

申请日：2024-11-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William C. Waldrop ,  Liang Chen ,  Shingo Mitsubori ,  Ryo Fujimaki ,  Atsuko Momma

IPC: G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

公开(公告)号：US20250094343A1

公开(公告)日：2025-03-20

申请号：US18782147

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

IPC: G06F12/02 ,  G06F13/16

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20250094339A1

公开(公告)日：2025-03-20

申请号：US18897806

申请日：2024-09-26

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello

IPC: G06F12/02 ,  G06F12/0891

Abstract: Methods, systems, techniques, and devices for smart factory reset procedures are described. In accordance with examples as disclosed herein, a memory system may receive one or more commands associated with a reset procedure. The memory system may identify, in response to the one or more commands, a first portion of one or more memory arrays of the memory system as storing user data and a second portion of the one or more memory arrays as storing data associated with an operating system. The memory system may update a mapping of the memory system based on identifying the first portion and the second portion. The memory system may transfer the data associated with the operating system to a third portion of the one or more memory arrays and perform an erase operation on a subset of physical addresses of the set of physical addresses.

公开(公告)号：US20250094262A1

公开(公告)日：2025-03-20

申请号：US18787655

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Victor Wong ,  Donald Morgan

IPC: G06F11/07

Abstract: Apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. The technology allows usage-based-disturbance (UBD) alerts to be externally communicated from a memory device without a dedicated external interface. Rather, UBD alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. UBD tracking occurs at the memory bank level, with corresponding independent UBD alert signals. These signals are efficiently combined to generate an overall UBD alert. A temporary backoff signal is generated when an overall UBD alert is sent. The backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent UBD alerts.