公开(公告)号：US20080268625A1

公开(公告)日：2008-10-30

申请号：US12023743

申请日：2008-01-31

Applicant: Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

Inventor： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

IPC: H01L21/425

CPC classification number: H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

Abstract: By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

Abstract translation: 通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺，可以基本上增加漏极和源极区域的垂直延伸，而不影响先前调节的沟道长度。 以这种方式，在SOI器件中，漏极和源极区域可以向下延伸到掩埋绝缘层，从而减小寄生电容，同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。 此外，在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。

公开(公告)号：US07442971B2

公开(公告)日：2008-10-28

申请号：US11045177

申请日：2005-01-28

Applicant: Frank Wirbeleit ,  Manfred Horstmann ,  Christian Hobert

Inventor： Frank Wirbeleit ,  Manfred Horstmann ,  Christian Hobert

IPC: H01L31/112

CPC classification number: H01L29/105 ,  G11C11/412 ,  H01L27/11 ,  H01L29/7838

Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

Abstract translation: 通过提供自偏压半导体开关，可以实现具有减少数量的各个有源元件的SRAM单元。 在特定实施例中，自偏置半导体器件可以以双通道场效应晶体管的形式提供，其允许形成具有小于六个晶体管元件的SRAM单元，并且在优选实施例中，具有少至两个单独的晶体管 元素。

公开(公告)号：US20080242040A1

公开(公告)日：2008-10-02

申请号：US11942400

申请日：2007-11-19

Applicant: Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

Inventor： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

IPC: H01L21/336

CPC classification number: H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

Abstract translation: 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

公开(公告)号：US07399663B2

公开(公告)日：2008-07-15

申请号：US11466572

申请日：2006-08-23

Applicant: Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

Inventor： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

IPC: H01L21/00 ,  H01L21/336

CPC classification number: H01L29/78684 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.

Abstract translation: 通过形成通过掩埋绝缘层的深凹槽并重新生长应变半导体材料，可以在SOI类晶体管中提供增强的应变产生机制。 因此，也可以通过整个有源层上的嵌入的应变半导体材料有效地产生应变，从而显着提高可以限定两个沟道区的晶体管器件的性能。

公开(公告)号：US20070254441A1

公开(公告)日：2007-11-01

申请号：US11566287

申请日：2006-12-04

Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L29/165 ,  H01L29/66583 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

Abstract translation: 形成场效应晶体管的方法包括提供包括半导体材料的双轴应变层的衬底。 在半导体材料的双轴应变层上形成栅电极。 在栅电极附近形成凸起的源区和升高的漏极区。 将掺杂剂材料的离子注入到凸起的源极区域和隆起的漏极区域中，以形成扩展的源极区域和延伸的漏极区域。 此外，在形成根据本发明的实施例的场效应晶体管的方法中，可以在半导体材料层的凹部中形成栅电极。 因此，可以获得其中位于沟道区附近的源极侧沟道接触区域和漏极侧沟道接触区域受到双轴应变的场效应晶体管。

公开(公告)号：US20070228377A1

公开(公告)日：2007-10-04

申请号：US11560896

申请日：2006-11-17

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel ,  Thomas Heller

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel ,  Thomas Heller

IPC: H01L29/76 ,  H01L21/84

CPC classification number: H01L21/823481 ,  H01L21/76243 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207

Abstract: By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.

Abstract translation: 通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能 通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。 因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

公开(公告)号：US07226859B2

公开(公告)日：2007-06-05

申请号：US10282720

申请日：2002-10-29

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L29/40

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract translation: 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着提高单个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

公开(公告)号：US07208397B2

公开(公告)日：2007-04-24

申请号：US11122740

申请日：2005-05-05

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Markus Lenski

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Markus Lenski

IPC: H01L21/425 ,  H01L21/22

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/66659 ,  H01L29/7835

Abstract: By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even completely be avoided, wherein a moderately reduced concentration gradient may further enhance the transistor performance.

Abstract translation: 通过提供场效应晶体管的光晕区域和延伸区域的非对称设计，对于给定的基本晶体管架构，晶体管性能可以显着增强。 特别地，由于提供了卤素区域，可能在源极侧产生具有PN结的陡峭浓度梯度的大的重叠区域，而可以显着地减少或甚至可以完全避免漏极重叠，其中适度地 降低的浓度梯度可进一步提高晶体管的性能。

公开(公告)号：US06905924B2

公开(公告)日：2005-06-14

申请号：US10629436

申请日：2003-07-29

Applicant: Gert Burbach ,  Manfred Horstmann ,  Thomas Feudel

Inventor： Gert Burbach ,  Manfred Horstmann ,  Thomas Feudel

IPC: H01L29/861 ,  H01L29/868 ,  H01L21/8234

CPC classification number: H01L29/868 ,  H01L29/861

Abstract: In an SOI diode structure, the conventional transistor-like MOS configuration is eliminated by replacing the polysilicon line by a completely dielectric region. This region may be used as an implantation mask to control a dopant gradient of a PN-junction that forms below the dielectric region. Moreover, during the salicide process, the dielectric region prevents the PN-junction from being shorted. Thus, a depletion of the active region caused by the MOS structure may be avoided. Therefore, the functioning of the PN-junction is maintained even for extremely thin semiconductor layers.

Abstract translation: 在SOI二极管结构中，通过将多晶硅线替换为完全介电区域来消除传统的晶体管状MOS结构。 该区域可以用作注入掩模以控制形成在电介质区域之下的PN结的掺杂剂梯度。 此外，在自对准硅化物工艺期间，电介质区域防止PN结短路。 因此，可以避免由MOS结构引起的有源区的耗尽。 因此，即使对于极薄的半导体层也保持PN结的功能。

公开(公告)号：US20050098818A1

公开(公告)日：2005-05-12

申请号：US11015061

申请日：2004-12-17

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek ,  Stephan Kruegel

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek ,  Stephan Kruegel

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/6659 ,  H01L21/2253 ,  H01L29/665 ,  H01L29/7833

Abstract: High-k dielectric spacer elements on the gate electrode of a field effects transistor in combination with an extension region that is formed by dopant diffusion from the high-k spacer elements into the underlying semiconductor region provides for an increased charge carrier density in the extension region. In this way, the limitation of the charge carrier density to approximately the solid solubility of dopants in the extension region may be overcome, thereby allowing extremely shallow extension regions without unduly compromising the transistor performance.

Abstract translation: 场效应晶体管的栅极上的高k电介质隔离元件与由高k隔离元件掺入到下面的半导体区域中的掺杂剂扩散形成的延伸区组合提供了延伸区中增加的电荷载流子密度 。 以这种方式，可以克服电荷载流子密度近似于扩散区域中掺杂剂的固溶度的限制，从而允许非常浅的延伸区域而不会不利地损害晶体管的性能。