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    Pipelined processor with microcontrol of register translation hardware
    11.
    发明授权
    Pipelined processor with microcontrol of register translation hardware 失效
    流水线处理器，具有寄存器转换硬件的微控制器

    公开(公告)号：US6073231A

    公开(公告)日：2000-06-06

    申请号：US819838

    申请日：1997-03-17

    申请人： Mark Bluhm ,  Mark W. Hervin

    发明人： Mark Bluhm ,  Mark W. Hervin

    IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/30134 ,  G06F9/226 ,  G06F9/384

    摘要： A microprocessor comprises one or more instruction pipelines having a plurality of stages for processing a stream of instructions, with one or more of said instructions referencing a set of logical registers. A plurality of physical registers are allocated to store data associated with the logical registers by register translation circuitry. The register translation circuitry is selectively controlled by the microcode or by hardware signals generated by one or more of the stages.

    摘要翻译： 微处理器包括具有用于处理指令流的多个级的一个或多个指令流水线，其中一个或多个指令引用一组逻辑寄存器。 分配多个物理寄存器以通过寄存器转换电路来存储与逻辑寄存器相关联的数据。 寄存器翻译电路由微代码或由一个或多个级产生的硬件信号选择性地控制。

    System and method of retiring store data from a write buffer
    12.
    发明授权
    System and method of retiring store data from a write buffer 失效
    从写缓冲区退出存储数据的系统和方法

    公开(公告)号：US5907860A

    公开(公告)日：1999-05-25

    申请号：US688900

    申请日：1996-07-31

    申请人： Raul A. Garibay, Jr. ,  Marc A. Quattromani ,  Mark Bluhm

    发明人： Raul A. Garibay, Jr. ,  Marc A. Quattromani ,  Mark Bluhm

    IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/04 ,  G06F12/08

    CPC分类号： G06F9/30043 ,  G06F12/0855 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3865 ,  G06F12/04

    摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes). are also disclosed.

    摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 用于处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。 也被披露。

    Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception
    13.
    发明授权
    Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception 失效
    使用有效位来识别将导致异常的指令的预取指令字节的异常处理

    公开(公告)号：US5479616A

    公开(公告)日：1995-12-26

    申请号：US863226

    申请日：1992-04-03

    申请人： Raul A. Garibay, Jr. ,  Mark Bluhm

    发明人： Raul A. Garibay, Jr. ,  Mark Bluhm

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3865 ,  G06F9/3802

    摘要： An exception handling system is used, in an exemplary embodiment, to provide exception handling for prefetched instruction bytes in a pipelined 486-type microprocessor. The microprocessor includes a prefetch unit (22) that controls the loading of a prefetch queue (24), including appending a valid bit to each prefetched instruction byte--this valid bit is conventionally used to notify an instruction decoder (26) that a transferred instruction byte is not valid (such as resulting from a change of flow), causing the decoder to signal a stall condition. According to the exception handling technique of the invention, if the prefetch unit detects that any of a selected number of exception conditions (such as limit violations and page faults) applies to a prefetched instruction byte, it invalidates that instruction byte by clearing the valid bit. When an invalid instruction byte is decoded, the decoder asserts a stall condition that can result from either: (a) the prefetch queue is invalid due to instruction bytes being unavailable or flushing in response to a branch, or (b) an exception condition. An exception processor (30) performs two basic functions: (a) monitoring the prefetch unit, and for any instruction byte for which a potential exception condition exists, storing in an exception status register the associated exception status information (for example, limit violation or page fault), and (b) monitoring the decoder to detect stall conditions. For each stall condition detected, the exception processor checks the exception status register for valid exception status information--if so, it invokes the appropriate exception handling routine. Thus, exception handling occurs at decode time, rather than after execution (requiring instruction abort and side effect handling).

    摘要翻译： 在示例性实施例中，使用异常处理系统为流水线486型微处理器中的预取指令字节提供异常处理。 微处理器包括一个预取单元（22），其控制预取队列（24）的加载，包括将有效位附加到每个预取指令字节 - 该有效位通常用于通知指令解码器（26）传送指令 字节无效（例如由于流程的改变而导致的），导致解码器发出失速状态信号。 根据本发明的异常处理技术，如果预取单元检测到选定数量的异常条件（例如限制违规和页面错误）中的任何一个应用于预取指令字节，则通过清除该有效位来使该指令字节无效 。 当无效指令字节被解码时，解码器断言可能由以下原因导致的停顿条件：（a）由于指令字节不可用或响应于分支而刷新，或（b）异常条件，预取队列无效。 异常处理器（30）执行两个基本功能：（a）监视预取单元以及存在潜在异常条件的任何指令字节，在异常状态寄存器中存储关联的异常状态信息（例如，限制违例或 页面故障），（b）监视解码器以检测失速状况。 对于检测到的每个失速条件，异常处理器检查异常状态寄存器以获取有效的异常状态信息 - 如果是，它调用适当的异常处理例程。 因此，异常处理在解码时发生，而不是执行后（需要指令中止和副作用处理）。

    PAY-FOR-ACCESS LEGAL RESEARCH SYSTEM WITH ACCESS TO OPEN WEB CONTENT
    15.
    发明申请
    PAY-FOR-ACCESS LEGAL RESEARCH SYSTEM WITH ACCESS TO OPEN WEB CONTENT 审中-公开
    付费访问法律研究系统访问开放的网页内容

    公开(公告)号：US20070027811A1

    公开(公告)日：2007-02-01

    申请号：US11422281

    申请日：2006-06-05

    申请人： Peter Jackson ,  Mark Bluhm

    发明人： Peter Jackson ,  Mark Bluhm

    IPC分类号： G06Q99/00

    CPC分类号： G06Q30/06 ,  G06F16/951 ,  G06Q30/02

    摘要： To facilitate legal research, companies, such as Thomson West provide subscription-based (pay-for-access) online information-retrieval systems. Seeking to improve these and related systems, the present inventors recognized researchers often need to access open web content that is outside their subscription-based system. Accordingly, the present inventors devised systems, methods, and software that automatically search for and identify open web documents in response to queries within the subscription-based system and/or automatically search for and identify pay-for-access content in response to receiving open web queries.

    摘要翻译： 为了方便法律研究，Thomson West等公司提供基于订阅（付费接入）在线信息检索系统。 为了改进这些和相关系统，本发明人认识到研究人员通常需要访问在其基于订阅的系统之外的开放web内容。 因此，本发明人设计出系统，方法和软件，其响应于基于订阅的系统内的查询自动地搜索和识别开放web文档，和/或响应于接收到开放的自动搜索和识别付费访问内容 网络查询。

    Systems, methods, and software for distributed loading of databases
    16.
    发明申请
    Systems, methods, and software for distributed loading of databases 有权

    公开(公告)号：US20060174101A1

    公开(公告)日：2006-08-03

    申请号：US11328499

    申请日：2006-01-09

    申请人： Mark Bluhm ,  Jon Verreaux

    发明人： Mark Bluhm ,  Jon Verreaux

    IPC分类号： G06F9/24

    CPC分类号： G06F17/30575 ,  Y10S707/99932

    摘要： The present inventors have devised one or more systems, methods, and software for distributed loading of information retrieval systems. One exemplary system includes two or more (at least two) load monitor servers that not only monitor and ensure completion of load tasks by individual load servers in a set of two or more load servers, but also provide for one load monitor to monitor performance of the another. Moreover, the exemplary system provides a service-level-agreement (SLA) data structure for each load server. The SLA data structure governs what types and priority levels of loading tasks will be performed for predetermined time periods.