公开(公告)号：US07576613B2

公开(公告)日：2009-08-18

申请号：US11709955

申请日：2007-02-23

申请人： Mu-Kyeng Jung ,  Soon-Kyun Shin

发明人： Mu-Kyeng Jung ,  Soon-Kyun Shin

IPC分类号： H03F3/04

CPC分类号： H03F1/223 ,  H03F3/345

摘要： A regulated cascode circuit includes a first MOS transistor of a first conductive type, a second MOS transistor of the first conductive type, a third MOS transistor of a second conductive type, a first current source and a second current source. The first MOS transistor is coupled between an output node and a first node. The second MOS transistor having a gate terminal for receiving a bias voltage is coupled between the first node and a second power supply voltage. The third MOS transistor is coupled between the first power supply voltage and a gate terminal of the first MOS transistor. The first current source is coupled between the gate terminal of the first MOS transistor. The second current source is coupled between the first power supply voltage and the output node.

摘要翻译： 调节共源共栅电路包括第一导电类型的第一MOS晶体管，第一导电类型的第二MOS晶体管，第二导电类型的第三MOS晶体管，第一电流源和第二电流源。 第一MOS晶体管耦合在输出节点和第一节点之间。 具有用于接收偏置电压的栅极端子的第二MOS晶体管被耦合在第一节点和第二电源电压之间。 第三MOS晶体管耦合在第一电源电压和第一MOS晶体管的栅极端子之间。 第一电流源耦合在第一MOS晶体管的栅极端之间。 第二电流源耦合在第一电源电压和输出节点之间。

公开(公告)号：US20080023761A1

公开(公告)日：2008-01-31

申请号：US11819606

申请日：2007-06-28

申请人： Mu-Kyeng Jung ,  Xiao Quan Wang ,  Bai-Sun Kong

发明人： Mu-Kyeng Jung ,  Xiao Quan Wang ,  Bai-Sun Kong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/66659

摘要： Semiconductor devices and methods of fabricating the same are provided. According to an example embodiment, a semiconductor device may include an active region disposed in a substrate and having first conductivity type impurity ions, a gate electrode crossing on the active region, a source region disposed within the active region at one a first side of the gate electrode, a drain region disposed within the active region at the a second side of the gate electrode, a source lightly doped drain (LDD) region disposed within the active region, extending toward the gate electrode from the source region, and having second conductivity type impurity ions, a drain LDD region disposed within the active region, extending toward the gate electrode from the drain region, and having the second conductivity type impurity ions in a concentration higher than the source LDD region, and a first halo region disposed within the active region, surrounding the source LDD region, and having the first conductivity type impurity ions.

摘要翻译： 提供半导体器件及其制造方法。 根据示例性实施例，半导体器件可以包括设置在衬底中并具有第一导电类型杂质离子的有源区，在有源区上交叉的栅电极，设置在有源区的第一侧的源极区 栅电极，设置在所述栅电极的第二侧的有源区内的漏极区，设置在所述有源区内的源极轻掺杂漏极（LDD）区，从所述源极区朝向所述栅电极延伸，并具有第二导电性 设置在有源区内的漏极LDD区域，从漏区延伸到栅电极，并且具有浓度高于源极LDD区域的第二导电型杂质离子，以及设置在该源极LDD区域内的第一晕圈区域 有源区，围绕源LDD区，并具有第一导电类型的杂质离子。

公开(公告)号：US20070200632A1

公开(公告)日：2007-08-30

申请号：US11709955

申请日：2007-02-23

申请人： Mu-Kyeng Jung ,  Soon-Kyun Shin

发明人： Mu-Kyeng Jung ,  Soon-Kyun Shin

IPC分类号： H03F1/22

CPC分类号： H03F1/223 ,  H03F3/345

摘要： A regulated cascode circuit includes a first MOS transistor of a first conductive type, a second MOS transistor of the first conductive type, a third MOS transistor of a second conductive type, a first current source and a second current source. The first MOS transistor is coupled between an output node and a first node. The second MOS transistor having a gate terminal for receiving a bias voltage is coupled between the first node and a second power supply voltage. The third MOS transistor is coupled between the first power supply voltage and a gate terminal of the first MOS transistor. The first current source is coupled between the gate terminal of the first MOS transistor. The second current source is coupled between the first power supply voltage and the output node.

摘要翻译： 调节共源共栅电路包括第一导电类型的第一MOS晶体管，第一导电类型的第二MOS晶体管，第二导电类型的第三MOS晶体管，第一电流源和第二电流源。 第一MOS晶体管耦合在输出节点和第一节点之间。 具有用于接收偏置电压的栅极端子的第二MOS晶体管被耦合在第一节点和第二电源电压之间。 第三MOS晶体管耦合在第一电源电压和第一MOS晶体管的栅极端子之间。 第一电流源耦合在第一MOS晶体管的栅极端之间。 第二电流源耦合在第一电源电压和输出节点之间。

公开(公告)号：US20070145452A1

公开(公告)日：2007-06-28

申请号：US11684865

申请日：2007-03-12

申请人： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

发明人： Byung-jun Oh ,  Kyung-tae Lee ,  Mu-kyeng Jung

IPC分类号： H01L29/94

CPC分类号： H01L21/76801 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0688 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit devices include an integrated circuit substrate and a conductive lower electrode layer of a capacitor on the integrated circuit substrate. A dielectric layer is on the lower electrode layer and a conductive upper electrode layer of the capacitor is on the dielectric layer. A first intermetal dielectric layer is on the upper electrode layer. The first intermetal dielectric layer includes at least one via hole extending to the upper electrode layer. A first conductive interconnection layer is on the at least one via hole of the first intermetal dielectric layer. A second intermetal dielectric layer is on the first intermetal dielectric layer. The second intermetal dielectric layer includes at least one via hole extending to the first conductive interconnection layer and at least partially exposing the at least one via hole of the first intermetal dielectric layer. A second conductive interconnection layer is provided in the at least one via hole of the second intermetal dielectric layer that electrically contacts the first conductive interconnection layer.

摘要翻译： 集成电路器件包括集成电路衬底和集成电路衬底上的电容器的导电下电极层。 介电层位于下电极层上，电容器的导电上电极层位于电介质层上。 第一金属间电介质层在上电极层上。 第一金属间电介质层包括延伸到上电极层的至少一个通孔。 第一导电互连层位于第一金属间电介质层的至少一个通孔上。 第二金属间介电层位于第一金属间电介质层上。 第二金属间电介质层包括延伸到第一导电互连层并且至少部分暴露第一金属间介电层的至少一个通孔的至少一个通孔。 第二导电互连层设置在与第一导电互连层电接触的第二金属间电介质层的至少一个通孔中。

公开(公告)号：US20080007338A1

公开(公告)日：2008-01-10

申请号：US11799993

申请日：2007-05-03

申请人： Mu-Kyeng Jung ,  Jae-Whui Kim ,  Bai-Sun Kong

发明人： Mu-Kyeng Jung ,  Jae-Whui Kim ,  Bai-Sun Kong

IPC分类号： H03F3/16 ,  H03F3/45

CPC分类号： H03F1/223 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2200/513 ,  H03F2203/45052 ,  H03F2203/45292 ,  H03F2203/45302 ,  H03F2203/45652

摘要： A regulated cascode circuit includes a first PMOS FET and a second PMOS FET connected in series between a first terminal that receives a first supply voltage and an output terminal, a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal that receives a second supply voltage, and a regulation circuit. The regulation circuit outputs a first control signal for stabilizing a voltage at a drain of the first PMOS FET to a gate of the second PMOS FET based on a voltage of the drain of the first PMOS FET and outputs a second control signal for stabilizing a voltage change in a source of the first NMOS FET to a gate of the first NMOS FET based on a voltage of the source of the first NMOS FET.

摘要翻译： 调节共源共栅电路包括串联连接在接收第一电源电压的第一端子和输出端子之间的第一PMOS FET和第二PMOS FET，串联连接在输出端子和第一NMOS FET之间的第一NMOS FET和第二NMOS FET 接收第二电源电压的第二端子和调节电路。 调节电路基于第一PMOS FET的漏极的电压输出用于将第一PMOS FET的漏极处的电压稳定到第二PMOS FET的栅极的第一控制信号，并输出用于稳定电压的第二控制信号 基于第一NMOS FET的源极的电压，将第一NMOS FET的源极改变到第一NMOS FET的栅极。

公开(公告)号：US07229875B2

公开(公告)日：2007-06-12

申请号：US10688077

申请日：2003-10-16

申请人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

IPC分类号： H01L21/8234

CPC分类号： H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

摘要翻译： 本发明的实施例包括具有高电容且具有改进的可制造性的MIM电容器。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US20060027876A1

公开(公告)日：2006-02-09

申请号：US11179434

申请日：2005-07-12

申请人： Mu-kyeng Jung ,  Hee-sung Kang ,  Hyuk-ju Ryu ,  Woo-young Chung ,  Kyung-soo Kim

发明人： Mu-kyeng Jung ,  Hee-sung Kang ,  Hyuk-ju Ryu ,  Woo-young Chung ,  Kyung-soo Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/7846 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/7833 ,  H01L29/7843

摘要： A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active region for forming a contact has a second width, a first gate arranged on the first device active region, a MOS transistor of a first conductivity type including a source/drain region of the first conductivity type formed in the first device active region, a second device active region having a third width greater than the first width, a second gate arranged on the second device active region, and a MOS transistor of a second conductivity type including a source/drain region of the second conductivity type formed in the second device active region.

摘要翻译： 具有改进性能的互补金属氧化物半导体（CMOS）器件包括包括至少一对晶体管有源区的第一器件有源区，其中一个晶体管有源区具有第一宽度，而用于形成接触的另一晶体管有源区具有第二宽度 布置在第一器件有源区上的第一栅极，第一导电类型的MOS晶体管，包括形成在第一器件有源区中的第一导电类型的源极/漏极区域，第三器件有源区域的第三宽度大于 所述第一宽度，布置在所述第二器件有源区上的第二栅极和包括形成在所述第二器件有源区中的所述第二导电类型的源极/漏极区的第二导电类型的MOS晶体管。

公开(公告)号：US07446607B2

公开(公告)日：2008-11-04

申请号：US11799993

申请日：2007-05-03

申请人： Mu-Kyeng Jung ,  Jae-Whui Kim ,  Bai-Sun Kong

发明人： Mu-Kyeng Jung ,  Jae-Whui Kim ,  Bai-Sun Kong

IPC分类号： H03F3/45

CPC分类号： H03F1/223 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2200/513 ,  H03F2203/45052 ,  H03F2203/45292 ,  H03F2203/45302 ,  H03F2203/45652

摘要： A regulated cascode circuit includes a first PMOS FET and a second PMOS FET connected in series between a first terminal that receives a first supply voltage and an output terminal, a first NMOS FET and a second NMOS FET connected in series between the output terminal and a second terminal that receives a second supply voltage, and a regulation circuit. The regulation circuit outputs a first control signal for stabilizing a voltage at a drain of the first PMOS FET to a gate of the second PMOS FET based on a voltage of the drain of the first PMOS FET and outputs a second control signal for stabilizing a voltage change in a source of the first NMOS FET to a gate of the first NMOS FET based on a voltage of the source of the first NMOS FET.

公开(公告)号：US20080032483A1

公开(公告)日：2008-02-07

申请号：US11973044

申请日：2007-10-05

申请人： Hyuk-Ju Ryu ,  Heon-Jong Shin ,  Hee-Sung Kang ,  Choong-Ryul Ryou ,  Mu-Kyeng Jung ,  Kyung-Soo Kim

发明人： Hyuk-Ju Ryu ,  Heon-Jong Shin ,  Hee-Sung Kang ,  Choong-Ryul Ryou ,  Mu-Kyeng Jung ,  Kyung-Soo Kim

IPC分类号： H01L21/78

CPC分类号： H01L21/76237 ,  H01L21/76224 ,  H01L21/823878

摘要： In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern. A trench isolation layer filling the trenches is then formed.

摘要翻译： 在沟槽隔离方法中，制备具有N-MOS区和P-MOS区的半导体衬底。 在N-MOS区形成露出N-MOS场区的第一掩模图案，在P-MOS区形成露出P-MOS场区的第二掩模图案。 形成第一光致抗蚀剂图案以覆盖P-MOS区并暴露N-MOS区。 使用第一掩模图案和第一光致抗蚀剂图案作为离子注入掩模将第一杂质离子注入到N-MOS区域中，从而在N-MOS场区域中形成第一杂质层。 在这种情况下，第一杂质层的一部分形成为延伸到第一掩模图案的下方。 去除第一光致抗蚀剂图案。 使用第一和第二掩模图案作为蚀刻掩模蚀刻半导体衬底，从而在N-MOS场区和P-MOS场区中形成沟槽，同时，形成第一杂质图案的第一杂质图案保留在第一 掩模图案。 然后形成填充沟槽的沟槽隔离层。