公开(公告)号：US06956773B2

公开(公告)日：2005-10-18

申请号：US10706306

申请日：2003-11-12

Applicant: Rino Micheloni ,  Roberto Ravasio

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A circuit (115,145,150), for programming a non-volatile memory device (100) having a plurality of memory cells (105), includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed. The driving elements are suitable to be supplied by a power supply unit (120,125), and a control means (145,150) controls the driving elements (115). The control means (145,150) includes means (150,205) for determining a residual capacity of the power supply unit, and a selecting means (145) selectively enables the driving elements (115) according to the residual capacity. A method of programming, an integrated circuit, and a computer system are also disclosed.

Abstract translation: 用于对具有多个存储单元（105）的非易失性存储器件（100）进行编程的电路（115,145,150）包括多个驱动元件（115），每个驱动元件用于向所选存储器单元施加编程脉冲， 程序。 驱动元件适于由电源单元（120,125）供电，并且控制装置（145,150）控制驱动元件（115）。 控制装置（145,150）包括用于确定电源单元的剩余容量的装置（150,205），以及选择装置（145）根据剩余容量有选择地启用驱动元件（115）。 还公开了编程方法，集成电路和计算机系统。

公开(公告)号：US5418849A

公开(公告)日：1995-05-23

申请号：US870179

申请日：1992-04-16

Applicant: Giacomo Cannalire ,  Giacomo Premoli ,  Roberto Ravasio

Inventor： Giacomo Cannalire ,  Giacomo Premoli ,  Roberto Ravasio

IPC: H04B3/23

CPC classification number: H04B3/23

Abstract: A procedure and device are described for cancellation of the echo produced in telephone connections with electrical time-variant characteristics such as for example those affected by phase roll. The echo canceller obtained in accordance with the procedure which is the object of this invention produces an estimate of the echo signal by means of appropriate digital filtering of the signal originated by the far-end talker. The estimated echo is then subtracted from the actual echo. Filtering is activated by an IIR digital filter whose adaptive coefficients are updated by use of an adaptive algorithm based on decimation of the square error. The high convergence speed of said algorithm in the calculation of the coefficient correction step allows a correct estimate of the echo even in case of connections affected by phase roll.

Abstract translation: 描述了用于消除在具有电时变特征的电话连接中产生的回波的过程和装置，例如受相位辊影响的那些。 根据作为本发明的目的的程序获得的回波消除器通过对由远端讲话者发起的信号的适当的数字滤波产生回波信号的估计。 然后从实际回波中减去估计的回波。 过滤由IIR数字滤波器激活，其自适应系数通过使用基于平方误差抽取的自适应算法来更新。 所述算法在系数校正步骤的计算中的高收敛速度允许即使在由相位滚动影响的连接的情况下也能正确估计回波。

公开(公告)号：US08065467B2

公开(公告)日：2011-11-22

申请号：US11844465

申请日：2007-08-24

Applicant: Rino Micheloni ,  Roberto Ravasio

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: G11C11/56 ,  G11C16/06 ,  G11C16/22 ,  G06F12/02

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641

Abstract: A solid state mass storage device having a first storage area portion and a second storage area portion. The mass storage device including accessing means adapted to cause data to be stored in the first storage area portion in one of: only in memory cells belonging to columns of a first collection or only to columns of a second collection such that memory cells of the first storage area portion belonging to the first or second collection are left unprogrammed; or only in memory cells of even rows or only memory cells of odd row such that the memory cells of the first storage area belonging to the even or to the odd rows are left unprogrammed; or only in memory cells such that memory cells that are immediately adjacent to said memory cells in said row and column are left unprogrammed.

Abstract translation: 一种具有第一存储区域部分和第二存储区域部分的固态大容量存储装置。 大容量存储装置包括适于使数据存储在第一存储区域部分中的存取装置，其中之一仅在属于第一集合的列的存储器单元中，或仅存储于第二集合的列，使得第一存储区的存储单元 属于第一或第二集合的存储区域部分未被编程; 或仅在奇数行的存储单元或仅存储单元的奇数行的存储单元中，使得属于偶数行或奇数行的第一存储区域的存储单元未被编程; 或仅在存储器单元中，使得与所述行和列中的所述存储器单元紧邻的存储器单元未被编程。

公开(公告)号：US07581153B2

公开(公告)日：2009-08-25

申请号：US11221584

申请日：2005-09-08

Applicant: Rino Micheloni ,  Roberto Ravasio ,  Angelo Bovino ,  Vincenzo Altieri

Inventor： Rino Micheloni ,  Roberto Ravasio ,  Angelo Bovino ,  Vincenzo Altieri

IPC: G11C29/00

CPC classification number: G06F11/1048

Abstract: A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

Abstract translation: 内存有一条总线用于数据，地址和命令。 数据寄存器耦合到总线以存储写入存储器和从存储器读取的数据，命令寄存器耦合到总线以接收存储器命令，并且地址寄存器耦合到总线以寻址存储器。 存储器还包括用于计算ECC的纠错码电路。 存储器被配置为响应于用于控制ECC电路的操作的外部命令，用于读取或写入与控制存储器数据的读取或写入的外部命令分离的ECC。 存储器还可以包括状态寄存器，其存储关于ECC的通过或失败的信息。

公开(公告)号：US20090185425A1

公开(公告)日：2009-07-23

申请号：US12016750

申请日：2008-01-18

Applicant: Roberto Ravasio ,  Detlev Richter ,  Gert Koebernik ,  Girolamo Gallo ,  Mirko Reissmann ,  Ramirez Xavier Veredas

Inventor： Roberto Ravasio ,  Detlev Richter ,  Gert Koebernik ,  Girolamo Gallo ,  Mirko Reissmann ,  Ramirez Xavier Veredas

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/26 ,  B82Y10/00 ,  G11C5/02 ,  G11C5/04 ,  G11C11/5614 ,  G11C11/5642 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/004 ,  G11C13/025 ,  G11C16/0483 ,  G11C2013/0054 ,  G11C2211/5634 ,  G11C2213/16 ,  G11C2213/71

Abstract: Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.

Abstract translation: 本发明的实施例一般涉及具有存储单元布置的集成电路和使用多个部分读数来读取存储单元状态的方法。 在本发明的实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括至少一个存储单元，该存储单元能够存储可预定数量的存储单元阈值区分的多个存储单元状态，以及控制器，被配置为读取存储单元状态的存储单元状态 至少一个存储器单元，其使用高于所述预定数量的存储单元阈值的多个参考电平，其中所述读取包括使用第一组多个参考电平的第一部分读取和使用第二组的第二部分读取 多个参考电平的第二组，其中多个参考电平的第二组包括与多个参考电平的第一组的参考电平不同的至少一个参考电平。

公开(公告)号：US07529136B2

公开(公告)日：2009-05-05

申请号：US11844480

申请日：2007-08-24

Applicant: Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio ,  Federico Pio

Inventor： Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio ,  Federico Pio

IPC: G11C16/04

CPC classification number: G11C16/344

Abstract: A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

Abstract translation: 一种用于操作闪存设备的方法。 存储器件包括存储器单元矩阵，每个存储器单元具有限定存储在存储器单元中的值的可编程阈值电压。 该方法包括以下步骤：擦除存储器单元块，以及在预定的压缩范围内压缩块的存储单元的阈值电压，其中压缩步骤包括：选择块写入的至少一个第一存储单元 目标值 将块的存储器单元的子集的阈值电压恢复到压缩范围，该子集包括与至少一个第一存储器相邻的块的至少一个第一存储器单元和/或至少一个第二存储器单元 细胞; 并且至少部分地将目标值写入至少一个第一存储单元。

公开(公告)号：US20080104477A1

公开(公告)日：2008-05-01

申请号：US12001294

申请日：2007-12-10

Applicant: Massimiliano Lunelli ,  Rino Micheloni ,  Roberto Ravasio ,  Alessia Marelli

Inventor： Massimiliano Lunelli ,  Rino Micheloni ,  Roberto Ravasio ,  Alessia Marelli

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/1575 ,  H03M13/13 ,  H03M13/15 ,  H03M13/19

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract translation: 描述了一种用于对编码为符号序列的数字信息进行纠错的方法和系统，例如存储在电子存储器系统中或从这些系统发送的数字信息或从这些系统发送和传送到这些系统的数字信息，提供包含一部分误差校正码的序列的传输， 这更可能是通过使用在接收时要恢复的奇偶校验矩阵的误差校正子的计算来传送的。 有利地，根据本发明的实施例，并入原始序列中的错误代码属于非布尔组。

公开(公告)号：US07366014B2

公开(公告)日：2008-04-29

申请号：US11495876

申请日：2006-07-28

Applicant: Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio

Inventor： Rino Micheloni ,  Luca Crippa ,  Roberto Ravasio

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A method for programming an electrically programmable memory including a plurality of memory cells arranged in individually-selectable memory cell sets each including at least one memory cell. The programming method includes causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state. Receiving a target value for the first data bits groups of the memory cells of the selected memory cells set. Receiving a target value for the second data bits groups of the memory cells of the selected memory cells set. After having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state jointly determined by the target values of the first and second data bits groups.

Abstract translation: 一种用于编程电可编程存储器的方法，包括布置在各自包括至少一个存储单元的可单独选择的存储单元组中的多个存储单元。 编程方法包括使所设置的选定存储单元的存储单元进入预定的开始编程状态。 接收所选存储器单元的存储单元的第一数据位组的目标值。 接收所选存储器单元的存储单元的第二数据位组的目标值。 在接收到第一和第二数据位组两者的目标值之后，将所选择的存储器单元的存储单元应用到所设置的编程顺序，以使所选择的存储单元组的存储器单元进入目标编程 状态由第一和第二数据位组的目标值联合确定。

公开(公告)号：US07362616B2

公开(公告)日：2008-04-22

申请号：US11495886

申请日：2006-07-28

Applicant: Angelo Bovino ,  Rino Micheloni ,  Roberto Ravasio

Inventor： Angelo Bovino ,  Rino Micheloni ,  Roberto Ravasio

IPC: G11C16/06

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A non-volatile memory device is proposed. The non-volatile memory device includes a plurality of memory cells each one having a programmable threshold voltage, and means for reading a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging a reading node associated with the selected memory cell with a charging voltage, means for biasing the selected memory cell with a biasing voltage, means for connecting the charged reading node with the biased selected memory cell, and means for sensing a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay, wherein for at least a second one of the reference voltages the biasing voltage is a second biasing voltage different from the second reference voltage, and the delay is a second delay different from the first delay.

Abstract translation: 提出了一种非易失性存储器件。 该非易失性存储器件包括多个具有可编程阈值电压的存储单元，以及用于针对每个所选择的存储器单元读取相对于多个参考电压的一组所选存储单元的装置，所述读取装置包括装置 用于利用充电电压对与所选择的存储器单元相关联的读取节点进行充电，用于利用偏置电压偏置所选择的存储单元的装置，用于将所述充电的读取节点与所偏置的选择的存储单元相连接的装置，以及用于感测所述存储单元 在来自所述连接的预定义延迟之后的所述读取节点，对于所述参考电压中的至少第一参考电压，所述偏置电压是等于所述第一参考电压的第一偏置电压，并且所述延迟是公共的第一延迟，其中对于至少第二个 的参考电压，偏置电压是与第二参考电压不同的第二偏置电压，并且延迟是第二延迟di 与第一次延迟不同。

公开(公告)号：US07336538B2

公开(公告)日：2008-02-26

申请号：US11495874

申请日：2006-07-28

Applicant: Luca Crippa ,  Chiara Missiroli ,  Roberto Ravasio ,  Rino Micheloni ,  Angelo Bovino

Inventor： Luca Crippa ,  Chiara Missiroli ,  Roberto Ravasio ,  Rino Micheloni ,  Angelo Bovino

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining means condition a potential of the coupling line based on the existing data value and the modified indication so as to cause the coupling line to take the program enabling potential or the program inhibition potential.

Abstract translation: 一种用于电可编程存储器的页面缓冲器，包括至少一个读/程序单元，其具有可操作地与至少一个所述位线相关联的耦合线，并且适于至少临时存储从或写入到 存储在所选存储单元组的存储单元中的第一或第二存储器页。 读/程序单元包括启用装置，用于通过使耦合线在程序使能电位和程序禁止电位之间采取一种方式来有选择地启用所选择的存储单元的编程状态的改变， 所选存储单元的第一组数据位和已存储在所选存储单元的第二组数据位中的现有数据值。 启用装置包括用于检索现有数据值的读取装置，用于接收目标数据值的指示的装置，用于将接收的目标数据值与所检索的现有数据值组合的组合装置，从而修改目标数据值的所述指示，从而 以获得修改的指示。 组合装置中的调节装置基于现有数据值和修改的指示来条件耦合线的电位，以使耦合线采取程序使能电位或程序禁止电位。