公开(公告)号：US06944046B2

公开(公告)日：2005-09-13

申请号：US10716565

申请日：2003-11-20

申请人： Ryu Ogiwara

发明人： Ryu Ogiwara

IPC分类号： G01R31/28 ,  G11C11/22 ,  G11C11/24 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  H01L21/8246 ,  H01L27/105

CPC分类号： G11C29/08 ,  G11C11/22

摘要： A ferroelectric memory comprising a plurality of memory cells each including a ferroelectric capacitor and a switch transistor, and operating in a test mode in which, after polarized data is written into the memory cell by applying a first electric potential difference between both electrodes of ferroelectric capacitors of the plurality of memory cells, and before reading of the polarized data from the memory cells is carried out, a second electric potential difference smaller than the first electric potential difference is applied between both the electrodes of the ferroelectric capacitors in a direction opposite to that at the time of writing the polarized data.

摘要翻译： 一种强电介质存储器，包括多个存储单元，每个存储单元包括铁电电容器和开关晶体管，并且在经过强电介质电容器的两个电极之间施加第一电位差而将偏振数据写入存储单元之后的测试模式下工作 并且在从存储单元读取偏振数据之前，在强电介质电容器的两个电极之间沿相反方向施加小于第一电位差的第二电位差 在写入极化数据时。

公开(公告)号：US06671200B2

公开(公告)日：2003-12-30

申请号：US10372886

申请日：2003-02-26

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值 在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US20120069663A1

公开(公告)日：2012-03-22

申请号：US13235389

申请日：2011-09-18

申请人： Kiyotaro ITAGAKI ,  Masaru Kito ,  Ryu Ogiwara ,  Hitoshi Iwai

发明人： Kiyotaro ITAGAKI ,  Masaru Kito ,  Ryu Ogiwara ,  Hitoshi Iwai

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/344 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

摘要翻译： 控制电路被配置为对选择的存储块中的所选择的单元单元执行擦除操作。 在擦除操作中，控制电路将包括在所选择的单元单元中的第一存储晶体管的主体的电压升高到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为 第二电压低于第一电压，并将等于或低于第二电压的第三电压施加到所选择的单元单元和未选择的单元单元中包括的第一存储晶体管的栅极。

公开(公告)号：US08134855B2

公开(公告)日：2012-03-13

申请号：US12404157

申请日：2009-03-13

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C29/50016

摘要： A driver circuit and a precharge circuit apply, in a test mode, a fixed potential to a bit-line, while applying a second plate-line voltage to a plate-line. Then, the bit-line is switched from a first bit-line precharge potential to a floating state, and the plate-line voltage is raised from the second plate-line voltage to a plate-line voltage.

摘要翻译： 在测试模式下，驱动电路和预充电电路将固定电位施加到位线，同时对板线施加第二板线电压。 然后，将位线从第一位线预充电电位切换到浮置状态，并且将板线电压从第二板线电压升高到板线电压。

公开(公告)号：US07902913B2

公开(公告)日：2011-03-08

申请号：US12618373

申请日：2009-11-13

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor having a first gate, a first source and a first drain; a second transistor having a second gate connected to the first gate, a second source connected to the first source and a second drain; a first diode connected between a ground and a V− node; a first resistor connected between the V− node and the first drain; a second diode and a second resistor connected between the ground and a V+ node; a third resistor connected between the V+ node and the first drain; an operational amplifier including input ports connected to the V+ node and the V− node and an output port connected to the first gate and the second gate; and a fourth resistor connected between the ground and the second drain.

摘要翻译： 根据本发明的一个方面，提供了一种参考电压产生电路，包括：具有第一栅极，第一源极和第一漏极的第一晶体管; 第二晶体管，具有连接到第一栅极的第二栅极，连接到第一源极和第二漏极的第二源极; 连接在地和V节点之间的第一二极管; 连接在V节点和第一漏极之间的第一电阻器; 连接在地和V +节点之间的第二二极管和第二电阻器; 连接在V +节点和第一漏极之间的第三电阻器; 运算放大器，包括连接到V +节点和V节点的输入端口以及连接到第一门极和第二门极的输出端口; 以及连接在地和第二漏极之间的第四电阻器。

公开(公告)号：US20110007579A1

公开(公告)日：2011-01-13

申请号：US12835615

申请日：2010-07-13

申请人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

发明人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： An internal voltage generator according to an embodiment generates a reference voltage used for detecting data stored in a semiconductor memory. A first AD converter is configured to convert an external voltage supplied to the semiconductor memory into a first digital value. A second AD converter is configured to convert a temperature characteristic voltage that changes depending on a temperature of the semiconductor memory into a second digital value. An adder is configured to receive a reference voltage trimming address that specifies the reference voltage, the first digital value, and the second digital value, and to output a third digital value obtained by performing a weighted addition of the reference voltage trimming address, the first digital value, and the second digital value. A driver is configured to output the reference voltage responding to the third digital value.

摘要翻译： 根据实施例的内部电压发生器产生用于检测存储在半导体存储器中的数据的参考电压。 第一AD转换器被配置为将提供给半导体存储器的外部电压转换为第一数字值。 第二AD转换器被配置为将根据半导体存储器的温度而变化的温度特性电压转换为第二数字值。 加法器被配置为接收指定参考电压，第一数字值和第二数字值的参考电压调整地址，并且输出通过执行参考电压调整地址的加权相加获得的第三数字值，第一 数字值和第二数字值。 驱动器被配置为响应于第三数字值输出参考电压。

公开(公告)号：US20100237931A1

公开(公告)日：2010-09-23

申请号：US12727123

申请日：2010-03-18

申请人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

发明人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

IPC分类号： G05F1/10

CPC分类号： G05F1/56 ,  G05F3/30 ,  H02M3/07 ,  H02M2003/072

摘要： An internal power supply voltage generation circuit 100 has a first charge pump circuit which steps up the external power supply voltage in response to the first clock signal and outputs a first stepped up voltage from the first voltage stepup output terminal; a second charge pump circuit which steps up the first stepup voltage in response to the second clock signal and outputs a second stepped up voltage from the second voltage stepup output terminal, the second stepped up voltage being higher than the first stepped up voltage; a first voltage stepdown circuit which steps down the first stepped up voltage and outputs a first stepped down voltage; and a second voltage stepdown circuit which steps down the second stepped up voltage and outputs a second stepped down voltage, the second stepped down voltage being higher than the first stepped up voltage.

摘要翻译： 内部电源电压产生电路100具有第一电荷泵电路，其响应于第一时钟信号升高外部电源电压，并从第一升压输出端子输出第一升压电压; 第二电荷泵电路，其响应于所述第二时钟信号升高所述第一升压电压，并且从所述第二升压输出端子输出第二升压电压，所述第二升压电压高于所述第一升压电压; 降低第一升压电压并输出第一降压电压的第一降压电路; 以及第二降压电路，其降低所述第二升压电压并输出第二降压电压，所述第二降压电压高于所述第一升压电压。

公开(公告)号：US07609099B2

公开(公告)日：2009-10-27

申请号：US11558156

申请日：2006-11-09

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03L7/00

CPC分类号： G01R19/16552

摘要： A circuit for detecting a power-on voltage of power supply encompasses a voltage divider connected between a first power supply and a second power supply, the potential of the second power supply is lower than the potential of the first power supply, and a detecting circuit connected between the first power supply and the second power supply. The voltage divider includes a series circuit encompassing a diode, a first dividing resistor connected to the diode and a second dividing resistor connected between the first dividing resistor and the second power supply. The detecting circuit includes a pMOS transistor whose gate electrode is connected to a connection node between the first dividing resistor and the second dividing resistor, a source resistor connected between the first power supply and the source electrode of the pMOS transistor and a drain resistor connected to the drain electrode of the pMOS transistor and the second power supply.

摘要翻译： 用于检测电源的通电电压的电路包括连接在第一电源和第二电源之间的分压器，第二电源的电位低于第一电源的电位，检测电路 连接在第一电源和第二电源之间。 分压器包括串联电路，其包括二极管，连接到二极管的第一分压电阻器和连接在第一分压电阻器和第二电源之间的第二分压电阻器。 该检测电路包括一个pMOS晶体管，其栅极连接到第一分压电阻和第二分压电阻之间的连接节点，源电阻连接在第一电源和pMOS晶体管的源电极之间，漏电阻连接到 pMOS晶体管的漏电极和第二电源。

公开(公告)号：US07426147B2

公开(公告)日：2008-09-16

申请号：US11531163

申请日：2006-09-12

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C11/22

摘要： A power supply voltage control circuit supplying a power supply voltage to a memory cell array, including word lines extending along row direction, bit lines extending along column direction, plate lines extending along the row direction, and a plurality of unit cells disposed at intersections of word lines and bit lines, includes a word line control circuit for supplying a first voltage to the word lines; and a plate line control circuit for supplying a second voltage to the plate lines; and the power supply voltage control circuit provides an amount of current flow from the first voltage so as to keep the first voltage potential almost constant during increasing a value of the second voltage in a power-on sequence, firstly increasing a value of the higher voltage of two potential voltages: the first voltage and the second voltage capacitive coupled, and then increasing a value of the lower second voltage.

摘要翻译： 1.一种电源电压控制电路，其向存储单元阵列供给电源电压，所述电源电压包括沿着行方向延伸的字线，沿着列方向延伸的位线，沿着行方向延伸的板条，以及设置在 字线和位线包括用于向字线提供第一电压的字线控制电路; 以及板线控制电路，用于向所述板线提供第二电压; 并且电源电压控制电路提供从第一电压的电流量，以便在增加通电序列中的第二电压的值时，保持第一电压电位几乎恒定，首先增加较高电压的值 的两个电位电压：第一电压和第二电压电容耦合，然后增加较低的第二电压的值。

公开(公告)号：US20080191792A1

公开(公告)日：2008-08-14

申请号：US12027699

申请日：2008-02-07

申请人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

发明人： Ryu OGIWARA ,  Daisaburo TAKASHIMA

IPC分类号： G05F1/10

CPC分类号： G05F1/465

摘要： Disclosed is a voltage generating circuit which steps down a voltage to output a stepped down voltage. The voltage generating circuit includes first and second transistors. The drains of the first and second transistors are connected to a higher voltage power supply. The gate of the first transistor is connected to the gate of the second transistor. The voltage of the gate of the first transistor is controlled by a control circuit such that a voltage of the source of the first transistor can reach a predetermined voltage. A stepped down voltage is outputted from the source of the second transistor.

摘要翻译： 公开了一种降压电压以输出降压的电压产生电路。 电压产生电路包括第一和第二晶体管。 第一和第二晶体管的漏极连接到较高电压的电源。 第一晶体管的栅极连接到第二晶体管的栅极。 第一晶体管的栅极的电压由控制电路控制，使得第一晶体管的源极的电压可以达到预定电压。 从第二晶体管的源极输出降压电压。