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22 条记录 (耗时 0.016 秒)

    Process For Cleaning Shield Surfaces In Deposition Systems
    12.
    发明申请
    Process For Cleaning Shield Surfaces In Deposition Systems 审中-公开
    沉积系统中清洁屏蔽表面的工艺

    公开(公告)号：US20140242500A1

    公开(公告)日：2014-08-28

    申请号：US14273419

    申请日：2014-05-08

    申请人： SEMATECH, INC. ,  ASAHI GLASS CO., LTD.

    发明人： Vibhu Jindal ,  Junichi Kageyama

    IPC分类号： G03F1/22 ,  B08B7/04 ,  C23C14/56

    CPC分类号： G03F1/22 ,  B08B7/04 ,  B82Y10/00 ,  B82Y40/00 ,  C23C14/34 ,  C23C14/564 ,  G03F1/60

    摘要： A process for cleaning and restoring deposition shield surfaces which results in a cleaned shield having a surface roughness of between about 200 microinches and about 500 microinches and a particle surface density of less than about 0.1 particles/mm2 of particles between about 1 micron and about 5 microns in size and no particles less than about 1 micron in size and method for use thereof is disclosed.

    摘要翻译： 一种用于清洁和恢复沉积屏蔽表面的方法，其导致具有约200微英寸至约500微英寸之间的表面粗糙度和小于约0.1微米/ mm 2的颗粒的颗粒表面密度在约1微米至约5微米之间的清洁屏蔽 公开了尺寸微米和尺寸小于约1微米的颗粒及其使用方法。

    Partial Die Process For Uniform Etch Loading Of Imprint Wafers
    14.
    发明申请
    Partial Die Process For Uniform Etch Loading Of Imprint Wafers 失效
    印版晶片均匀刻蚀加工的部分模切工艺

    公开(公告)号：US20130122708A1

    公开(公告)日：2013-05-16

    申请号：US13734593

    申请日：2013-01-04

    申请人： SEMATECH, INC.

    发明人： Matt Malloy

    IPC分类号： H01L21/306 ,  H01L21/30

    CPC分类号： H01L21/306 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/30

    摘要： Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.

    摘要翻译： 公开了在光刻工艺中由半导体芯片的部分裸片的方便处理的方法，系统和装置。 实施例利用不与部分模具进行物理接触的压印式模板进行曝光。 在一个实施例中，公开了一种具有至少一个完整管芯和至少一个部分管芯的半导体工艺。 部分地通过使用蚀刻工艺来制造半导体芯片，该蚀刻工艺利用当压印模板与被分配到至少一个完整裸片上的抗蚀剂接触时构造成暴露于至少一个全裸片的印模模板 。 此外，半导体芯片的至少一个部分裸片被配置为暴露于压印模板，而不将模板接触抗蚀剂分配到至少一个部分裸片上。

    Tunneling field-effect transistor with direct tunneling for enhanced tunneling current
    17.
    发明授权
    Tunneling field-effect transistor with direct tunneling for enhanced tunneling current 有权
    隧穿场效应晶体管，具有直接隧道效应，用于增强隧穿电流

    公开(公告)号：US09029218B2

    公开(公告)日：2015-05-12

    申请号：US13856649

    申请日：2013-04-04

    申请人： Sematech, Inc.

    发明人： Wei-Yip Loh ,  Brian Coss ,  Kanghoon Jeon

    IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66477 ,  H01L29/7391 ,  H01L29/78

    摘要： Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

    摘要翻译： 在源极和漏极区之间具有突变结的水平和垂直隧道场效应晶体管（TFET）增加了载流子（例如，电子和空穴）的直接隧穿的概率。 增加的概率允许在具有突变结的TFET中更高的电流可实现。 可以通过在源极和漏极区域之间的电流路径中放置介电层或电介质层和半导体层来形成突变结。 电介质层可以是低介电常数氧化物，例如氧化硅，氧化镧，氧化锆或氧化铝。

    Metal alloy with an abrupt interface to III-V semiconductor
    18.
    发明授权
    Metal alloy with an abrupt interface to III-V semiconductor 有权
    与III-V半导体突然接口的金属合金

    公开(公告)号：US08829567B2

    公开(公告)日：2014-09-09

    申请号：US13729592

    申请日：2012-12-28

    申请人： Sematech, Inc.

    发明人： Rinus Tek Po Lee ,  Tae Woo Kim ,  Man Hoi Wong ,  Richard Hill

    IPC分类号： H01L21/02 ,  H01L21/00 ,  H01L29/205

    CPC分类号： H01L29/205 ,  H01L21/28575 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66522

    摘要： Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.

    摘要翻译： 具有包括n型III-V半导体材料的第一层和包括M（InP）（InGaAs）合金）的第二层的半导体结构，其中M选自Ni，Pt，Pd，Co，Ti，Zr，Y， Mo，Ru，Ir，Sb，In，Dy，Tb，Er，Yb和Te及其组合。 半导体结构在第一和第二层之间具有基本平坦的界面。 还公开了制造半导体结构的方法，以及降低接触面的界面粗糙度和/或薄层电阻的方法。

    Coating Of Shield Surfaces In Deposition Systems
    19.
    发明申请
    Coating Of Shield Surfaces In Deposition Systems 审中-公开
    在沉积系统中涂覆屏蔽表面

    公开(公告)号：US20140242501A1

    公开(公告)日：2014-08-28

    申请号：US14273426

    申请日：2014-05-08

    申请人： SEMATECH, INC. ,  ASAHI GLASS CO., LTD.

    发明人： Vibhu Jindal ,  Junichi Kageyama

    IPC分类号： C23C14/56 ,  G03F1/22 ,  C23C14/35

    CPC分类号： C23C14/564 ,  B82Y10/00 ,  B82Y40/00 ,  C23C14/34 ,  C23C14/35 ,  G03F1/22 ,  G03F1/60

    摘要： A deposition chamber shield having a stainless steel coating of from about 100 microns to about 250 microns thick wherein the coated shield has a surface roughness of between about 300 microinches and about 800 microinches and a surface particle density of less than about 0.1 particles/mm2 of particles between about 1 micron and about 5 microns in size and no particles below about 1 micron in size, and process for production thereof is disclosed.

    摘要翻译： 一种沉积室屏蔽，其具有约100微米至约250微米厚的不锈钢涂层，其中涂覆的屏蔽物具有约300微英寸至约800微英寸的表面粗糙度和小于约0.1微米/ mm 2的表面颗粒密度 公开了尺寸为约1微米至约5微米且尺寸小于约1微米的颗粒的颗粒及其生产方法。

    EXTREME ULTRAVIOLET LITHOGRAPHY (EUVL) ALTERNATING PHASE SHIFT MASK
    20.
    发明申请
    EXTREME ULTRAVIOLET LITHOGRAPHY (EUVL) ALTERNATING PHASE SHIFT MASK 审中-公开
    极端超紫外线（EUVL）替代相位移

    公开(公告)号：US20140170533A1

    公开(公告)日：2014-06-19

    申请号：US13719621

    申请日：2012-12-19

    申请人： GLOBAL FOUNDRIES INC. ,  SEMATECH, INC.

    发明人： Lei Sun ,  Pawitter S. Mangat ,  Vibhu Jindal ,  Obert R. Wood, II

    IPC分类号： G03F1/22

    CPC分类号： G03F1/22

    摘要： An alternating phase shift mask for use with extreme ultraviolet lithography is provided. A substrate with a planar top surface is used as a base for the phase shift mask. A spacer layer serves as a Fabry-Perot cavity for controlling the phase shift difference between two adjacent surfaces of the phase shift mask and controlling the reflectivity from the top of the second multilayer. A protective layer serves as an etch stop layer to protect a first multilayer region in certain regions of the phase shift mask, while other regions of the phase shift mask utilize a second multilayer region for achieving a phase shift difference. Some embodiments may further include an absorber layer region to provide areas with no reflectance, in addition to the areas of alternating phase shift. Embodiments of the present invention may be used to monitor the focus and aberration of a lithography tool.

    摘要翻译： 提供了一种用于极紫外光刻的交替相移掩模。 具有平面顶表面的基板用作相移掩模的基底。 间隔层用作法布里 - 珀罗腔，用于控制相移掩模的两个相邻表面之间的相移差，并控制来自第二多层的顶部的反射率。 保护层用作蚀刻停止层以保护相移掩模的某些区域中的第一多层区域，而相移掩模的其它区域利用第二多层区域来实现相移差。 除了交替相移的区域之外，一些实施例还可以包括提供没有反射率的区域的吸收层区域。 本发明的实施例可以用于监测光刻工具的焦点和像差。