公开(公告)号：US20240395944A1

公开(公告)日：2024-11-28

申请号：US18793415

申请日：2024-08-02

Applicant: Socionext Inc.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US12142606B2

公开(公告)日：2024-11-12

申请号：US17706117

申请日：2022-03-28

Applicant: Socionext Inc.

Inventor： Junji Iwahori

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423

Abstract: A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.

公开(公告)号：US12141936B2

公开(公告)日：2024-11-12

申请号：US17825781

申请日：2022-05-26

Applicant: Socionext Inc.

Inventor： Kazuyuki Ohhashi

IPC: G06T3/00 ,  G06T3/08 ,  G06T3/14 ,  G06T7/70

Abstract: An image processing apparatus is disclosed. The image processing apparatus includes a processor connected to a memory. The processor functions as a deformation unit. The deformation unit serves to deform a reference projection screen that is a projection screen of a surrounding image of a moving object. The reference projection screen is deformed by using position information in which detection points around the moving object are accumulated and using self-location information of the moving object.

公开(公告)号：US12119301B2

公开(公告)日：2024-10-15

申请号：US17716299

申请日：2022-04-08

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Atsushi Okamoto ,  Hirotaka Takeno

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US20240332304A1

公开(公告)日：2024-10-03

申请号：US18738947

申请日：2024-06-10

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO ,  Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11881

Abstract: First and second semiconductor chips are stacked one upon the other with the back face of the first semiconductor chip opposed to the principal face of the second semiconductor chip. The first semiconductor chip includes: first and second power lines formed in a buried interconnect layer, extending in the X direction, and adjoining each other in the Y direction; first and second contacts provided between the first and second power lines and the chip back face; and a third contact provided between a signal line and the chip back face. The third contact is located between the first and second power lines in the Y direction, and at a position different from the positions of the first and second contacts in the X direction, in planar view.

公开(公告)号：US12087735B2

公开(公告)日：2024-09-10

申请号：US17210743

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Hirotaka Takeno ,  Wenzhen Wang ,  Atsushi Okamoto

IPC: H01L25/065 ,  G11C5/14 ,  H01L27/02 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L27/0207 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.

公开(公告)号：US12080804B2

公开(公告)日：2024-09-03

申请号：US18315317

申请日：2023-05-10

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L29/786 ,  B82Y10/00 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/775

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

公开(公告)号：US20240290715A1

公开(公告)日：2024-08-29

申请号：US18399335

申请日：2023-12-28

Applicant: Socionext Inc.

Inventor： Yasuhiko MAKI

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06541

Abstract: In a semiconductor integrated circuit device, a first semiconductor chip includes: a buried power rail that supplies first power; and a power line that is provided in a layer above the buried power rail and supplies second power. The buried power rail receives supply of the first power from the back face of the first semiconductor chip via a first through electrode, and the power line receives supply of the second power from the back face of the first semiconductor chip via a second through electrode. The cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode.

公开(公告)号：US20240288281A1

公开(公告)日：2024-08-29

申请号：US18656055

申请日：2024-05-06

Applicant: Socionext Inc.

Inventor： Kazuyuki OHHASHI

IPC: G01C21/00 ,  G06T1/60 ,  G06T7/73 ,  G06V10/40 ,  G06V20/58

CPC classification number: G01C21/3837 ,  G06T1/60 ,  G06T7/73 ,  G06V10/40 ,  G06V20/58

Abstract: According to one embodiment, an information processing device includes a buffer and a VSLAM processor. The buffer buffers image data of surroundings of a moving body obtained by an imaging unit of the moving body, and transmits extracted image data extracted based on extracted image determination information from among the buffered image data. The VSLAM processor executes a VSLAM process by using the extracted image data.

公开(公告)号：US20240274536A1

公开(公告)日：2024-08-15

申请号：US18432890

申请日：2024-02-05

Applicant: SOCIONEXT INC.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L27/0922 ,  H01L27/0924

Abstract: A semiconductor device includes: a substrate; a circuit region provided on the substrate; a first power supply line and a second power supply line, positioned in the circuit region; a first fin and a second fin, each extending in a first direction in the circuit region, in plan view, and protruding from the substrate; a first power supply switching circuit, positioned in the circuit region and including a first transistor formed with the first fin, the first circuit electrically connecting the first and second power supply lines, and the first fin extending in the first power supply switching circuit without cutting; and a second power supply switching circuit, positioned in the circuit region and including a second transistor formed with the second fin, the second circuit electrically connecting the first and second power supply lines, and including a fin-cut part in which the second fin is cut.