公开(公告)号：US08361859B2

公开(公告)日：2013-01-29

申请号：US12942289

申请日：2010-11-09

Applicant: Thomas N. Adam ,  Stephen W. Bedell ,  Abhishek Dube ,  Eric C. T. Harley ,  Judson R. Holt ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Matthew W. Stoker ,  Keith H. Tabakman

Inventor： Thomas N. Adam ,  Stephen W. Bedell ,  Abhishek Dube ,  Eric C. T. Harley ,  Judson R. Holt ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC: H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.

Abstract translation: 在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。 结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

公开(公告)号：US20120252216A1

公开(公告)日：2012-10-04

申请号：US13075657

申请日：2011-03-30

Applicant: Thomas N. Adam ,  Stephen W. Bedell ,  Alexander Reznicek ,  Devendra K. Sadana

Inventor： Thomas N. Adam ,  Stephen W. Bedell ,  Alexander Reznicek ,  Devendra K. Sadana

IPC: H01L21/302

CPC classification number: H01L21/02046

Abstract: Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.

Abstract translation: 提供低温原位技术用于在CMOS外延处理期间从硅表面去除氧化物。 通过在硅表面上沉积SiGe层，从具有硅表面的半导体晶片去除氧化物; 在低于700℃（以上，例如约450℃）的温度下，从硅表面蚀刻SiGe层; 并重复沉积和蚀刻步骤多次，直到污染物基本上从硅表面除去。 在一个变型中，沉积层包括IV族半导体材料和/或其合金。

公开(公告)号：US20120146050A1

公开(公告)日：2012-06-14

申请号：US12967323

申请日：2010-12-14

Applicant: THOMAS N. ADAM ,  STEPHEN W. BEDELL ,  ERIC C. HARLEY ,  JUDSON R. HOLT ,  ANITA MADAN ,  CONAL E. MURRAY ,  TERESA L. PINTO

Inventor： THOMAS N. ADAM ,  STEPHEN W. BEDELL ,  ERIC C. HARLEY ,  JUDSON R. HOLT ,  ANITA MADAN ,  CONAL E. MURRAY ,  TERESA L. PINTO

IPC: H01L29/161 ,  G01N23/20

CPC classification number: H01L29/1054 ,  G01N23/207 ,  G01N2223/607 ,  G01N2223/6116 ,  H01L21/823807 ,  H01L22/12

Abstract: A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices.

Abstract translation: 在包括半导体器件的衬底上提供的单元结构的周期性阵列上进行通过X射线衍射的晶格间距的直接测量。 每个单位结构包括单晶应变材料区域和至少一个应力产生材料区域。 例如，单晶应变材料区域可以是模拟场效应晶体管的沟道的结构，并且所述至少一个应力产生材料区域可以是与单晶应变材料区域外延对准的单晶半导体区域。 可以在各种处理状态下原位执行直接测量，以提供在实际半导体器件中场效应晶体管中的应变的在线监测。

公开(公告)号：US20120009766A1

公开(公告)日：2012-01-12

申请号：US12830626

申请日：2010-07-06

Applicant: Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

Inventor： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC: H01L21/20

CPC classification number: H01L29/1054 ,  H01L29/7833

Abstract: A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.

Abstract translation: 提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。 在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸， 下层SOI层的平面晶格参数。 在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸， 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。

公开(公告)号：US07875908B2

公开(公告)日：2011-01-25

申请号：US12060615

申请日：2008-04-01

Applicant: Thomas N. Adam ,  Rajendran Krishnasamy

Inventor： Thomas N. Adam ,  Rajendran Krishnasamy

IPC: H01L31/072

CPC classification number: H01L29/7378 ,  H01L29/1004 ,  H01L29/66242

Abstract: Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.

Abstract translation: 双极晶体管和形成双极晶体管的方法。 该方法包括在硅衬底中形成P型集电体; 在集电体上形成本征碱，本征碱包括第一N型掺杂剂物质，锗和碳; 在本征基极的第一区域和第二区域上形成N型外部基极，在与集电体相邻的电介质上的集电极和第二区域之上的第一区域，含有或不含有碳的N型外部碱基; 以及在本征基底的第一区域上形成P型发射体。

公开(公告)号：US07759702B2

公开(公告)日：2010-07-20

申请号：US11969448

申请日：2008-01-04

Applicant: Thomas N. Adam ,  Rajendran Krishnasamy

Inventor： Thomas N. Adam ,  Rajendran Krishnasamy

IPC: H01L29/06

CPC classification number: H01L29/7371 ,  H01L21/82285 ,  H01L21/823878 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/1203 ,  H01L29/045

Abstract: A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation . The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation in addition to silicon crystalline orientation to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation may be disposed on crystalline orientation . Alternatively, the region of silicon crystalline orientation may be disposed on crystalline orientation .

Abstract translation: 公开了一种制造异质结双极晶体管（HBT）的方法，其中HBT具有结合设置在包含硅晶取向<110>的衬底上的异质结双极结构的结构。 异质结双极结构可以包括发射极，基极和集电极。 衬底可以包括浅沟槽隔离（STI）区域和设置有集电极的深沟槽区域。 除了硅晶体取向<110>之外，衬底可以包括硅晶体取向<100>的区域，以通过使用混合取向技术（HOT）形成复合衬底。 结晶取向区域<100>可以设置在晶体取向110上。 或者，硅结晶取向区域<110>可以以结晶取向<100>设置。

公开(公告)号：US20090302348A1

公开(公告)日：2009-12-10

申请号：US12136195

申请日：2008-06-10

Applicant: Thomas N. Adam ,  Judson R. Holt ,  Thomas A. Wallner

Inventor： Thomas N. Adam ,  Judson R. Holt ,  Thomas A. Wallner

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region.

Abstract translation: 提供了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：栅极导体，设置在一对电介质间隔物之间​​的半导体衬底之上，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域， 区域覆盖电介质间隔物以形成通道区域的底切区域; 以及设置在半导体衬底的凹陷区域中的外延源极和漏极区域，并且在电介质间隔物的下方横向延伸到沟道区域的底切区域中。

公开(公告)号：US20090173941A1

公开(公告)日：2009-07-09

申请号：US11970592

申请日：2008-01-08

Applicant: Thomas N. Adam ,  Ashima B. Chakravarti ,  Eric C. T. Harley ,  Judson R. Holt

Inventor： Thomas N. Adam ,  Ashima B. Chakravarti ,  Eric C. T. Harley ,  Judson R. Holt

IPC: H01L29/04 ,  H01L21/205

CPC classification number: H01L29/66545 ,  H01L21/0237 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66553

Abstract: Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.

Abstract translation: 制造具有设置在半导体结构的基板的表面上的非外延薄膜的半导体结构的方法; 并且公开了由其形成的半导体结构。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。

公开(公告)号：US20080290370A1

公开(公告)日：2008-11-27

申请号：US11804773

申请日：2007-05-21

Applicant: Jin-Ping Han ,  Henry Utomo ,  O Sung Kwon ,  Oh Jung Kwon ,  Judson Robert Holt ,  Thomas N. Adam

Inventor： Jin-Ping Han ,  Henry Utomo ,  O Sung Kwon ,  Oh Jung Kwon ,  Judson Robert Holt ,  Thomas N. Adam

IPC: H01L29/778 ,  H01L21/20 ,  H01L21/336

CPC classification number: H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.

Abstract translation: 公开了半导体器件及其制造方法。 在优选实施例中，制造半导体器件的方法包括提供工件，并在工件中形成凹部。 凹部具有第一尺寸的深度。 在凹部中形成第一半导体材料以将中心区域中的凹部部分地填充到具有第二尺寸的高度。 第二维度约为第一维度的一半或更大。 第二半导体材料形成在凹部中的第一半导体材料上，以完全填充凹部，第二半导体材料不同于第一半导体材料。

公开(公告)号：US20070284674A1

公开(公告)日：2007-12-13

申请号：US11423286

申请日：2006-06-09

Applicant: Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Kathryn T. Schonenberg ,  Thomas A. Wallner

Inventor： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Kathryn T. Schonenberg ,  Thomas A. Wallner

IPC: H01L29/94

CPC classification number: H01L29/16 ,  H01L29/66242 ,  H01L29/7371

Abstract: A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base layer extending over a portion of the porous silicon region to form an extrinsic base; and forming an isolation region in the porous silicon region. The method is applicable to forming an HBT having a structure including a crystalline silicon intrinsic base extending beyond a collector region and extending over an isolation region to form a continuous intrinsic-to-extrinsic base conduction path of low resistance. The HBT has improved performance by having a smaller collector to intrinsic base interface and larger intrinsic base to extrinsic base interface.

Abstract translation: 公开了使用多孔硅形成隔离区域的方法和相关结构。 该方法的一个实施例可以包括形成收集区域; 在集电区域形成多孔硅区域; 在所述集电极区上形成晶体硅本征基极层，所述本征基极层在所述多孔硅区域的一部分上延伸以形成外部基极; 以及在所述多孔硅区域中形成隔离区域。 该方法适用于形成具有包括结晶硅本征基底的结构的HBT，该晶体硅本征基极延伸超过集电极区域并在隔离区域上延伸以形成具有低电阻的连续本征至外在的基极传导路径。 HBT通过使内部基本接口具有较小的集电极和较大的内在基极到外部基极接口来提高性能。