公开(公告)号：US07839699B2

公开(公告)日：2010-11-23

申请号：US12050386

申请日：2008-03-18

申请人： Tomoki Higashi ,  Takashi Ohsawa

发明人： Tomoki Higashi ,  Takashi Ohsawa

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C5/14

CPC分类号： H01L29/7841 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C11/404 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5006 ,  G11C2211/4016

摘要： This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines.

摘要翻译： 本公开涉及一种半导体存储器件，包括：具有二维排列的存储单元的存储单元阵列; 连接到存储单元阵列的行的存储单元的字线; 连接到存储单元阵列的列的存储单元的位线; 连接到位线的感测放大器，以及检测存储在存储单元中的数据; 测试垫，其从电源通过预定的参考电流，并且基于所述参考电流传输参考电压; 以及连接在电源和测试焊盘之间并且插入电源和位线之间的测试电路，测试电路经由位线根据参考电压使测试电流通过。

公开(公告)号：US07638840B2

公开(公告)日：2009-12-29

申请号：US12187820

申请日：2008-08-07

申请人： Takashi Ohsawa

发明人： Takashi Ohsawa

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/1203

摘要： A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.

摘要翻译： 根据本发明的半导体存储装置，包括：通过掩埋绝缘层在基板上形成的第一半导体层; 具有形成在第一半导体层上的浮动通道体的FBC（浮体体池），在通道体的第一面侧形成通道的主栅极和形成为在第二面上电容耦合的辅助栅极 在第一面的相对侧; 形成在第一半导体层上的逻辑电路，其通过绝缘膜与FBC分开，该绝缘膜传送用于FBC的信号; 位于FBC下方并沿着掩埋绝缘膜的下表面形成的第二半导体层; 以及第三半导体层，其位于所述逻辑电路的下方并且沿着所述掩埋绝缘膜的下表面形成，其中所述第二和第三半导体层被设定为彼此不同的电位。

公开(公告)号：US07609551B2

公开(公告)日：2009-10-27

申请号：US11860956

申请日：2007-09-25

申请人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoaki Shino ,  Akihiro Nitayama ,  Takeshi Hamamoto ,  Hideaki Aochi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： G11C14/00 ,  G11C16/04

CPC分类号： H01L29/792 ,  G11C11/404 ,  G11C11/4074 ,  G11C14/0018 ,  G11C2211/4016 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42344 ,  H01L29/785 ,  H01L29/78648

摘要： This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

摘要翻译： 本公开涉及包含电荷捕获膜的存储器; 栅极绝缘膜; 电荷捕获膜上的后门; 栅极绝缘膜上的前门; 以及设置在漏极和源极之间的体区，其中所述存储器包括用于根据所述身体区域中的多数载体的数量存储数据的第一存储状态和用于根据所述体内区域中的电荷量存储数据的第二存储状态 通过将身体区域中的多数载体的数量转换为电荷俘获膜中的电荷量或从第二存储状态到第一存储器，将存储器从第一存储状态转移到第二存储状态 通过将电荷俘获膜中的电荷量转换成体区中的多数载体的数量来进行状态。

公开(公告)号：US20090168576A1

公开(公告)日：2009-07-02

申请号：US12343805

申请日：2008-12-24

申请人： Katsuyuki FUJITA ,  Takashi OHSAWA

发明人： Katsuyuki FUJITA ,  Takashi OHSAWA

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C11/404 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

摘要： A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each being connected to second bit lines corresponding to two memory cell arrays at both sides of the second sense amplifier; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays.

摘要翻译： 存储器包括：布置在存储单元阵列的布置的第一间隔中的第一读出放大器，每个存储单元阵列连接到对应于设置在第一读出放大器两侧的两个存储单元阵列的第一位线; 第二读出放大器布置在存储单元阵列的布置的第二间隔中，每个第二读出放大器连接到对应于第二读出放大器两侧的两个存储单元阵列的第二位线; 在存储单元阵列的布置的两端附近提供的边缘阵列，边缘阵列仅生成参考数据; 以及设置在存储单元阵列和边缘阵列的布置之间的边缘读出放大器，其中边缘读出放大器基于来自边缘阵列之一的参考数据来检测来自存储单元阵列的一端的存储单元阵列的数据。

公开(公告)号：US20090108767A1

公开(公告)日：2009-04-30

申请号：US11922852

申请日：2006-05-31

申请人： Yasuhiko Kohno ,  Takashi Ohsawa

发明人： Yasuhiko Kohno ,  Takashi Ohsawa

IPC分类号： H02M3/22 ,  H05B41/26

CPC分类号： H02M3/285 ,  H02M2001/0058 ,  H05B41/288 ,  H05B41/2882 ,  Y02B70/1491

摘要： A DC/DC converter device according to the present invention includes a plurality of resonant DC/DC converters 3, connected in parallel, and a timing control circuit 5 driving the plurality of resonant DC/DC converters at substantially the same frequency with a phase shift.

摘要翻译： 根据本发明的DC / DC转换器装置包括并联连接的多个谐振DC / DC转换器3和定时控制电路5，其基本上以相移的频率驱动多个谐振DC / DC转换器 。

公开(公告)号：US20090009279A1

公开(公告)日：2009-01-08

申请号：US12223528

申请日：2006-11-21

申请人： Yusuke Umeda ,  Keiko Konishi ,  Takashi Ohsawa

发明人： Yusuke Umeda ,  Keiko Konishi ,  Takashi Ohsawa

IPC分类号： H01F27/24 ,  H05B41/02

CPC分类号： H05B41/04 ,  H01F27/325 ,  H01F27/326 ,  H01F38/10 ,  H01F2005/022

摘要： A high-voltage generating transformer for a discharge lamp lighting apparatus according to the present invention includes a rodlike core; a secondary winding bobbin that is divided into a plurality of sections, and where the core is disposed in the central portion thereof; a secondary winding part wound on the secondary winding bobbin, divided between the plurality of sections of the bobbin; a primary winding bobbin disposed around the outer periphery of the secondary winding part; and a primary winding part wound on the primary winding bobbin; wherein the primary winding bobbin is changed in thickness every section or every plurality of sections of the second winding part such that the bobbin has a thickened thickness on the side where the potential difference between the primary winding part and the secondary winding part is high, and the bobbin has a thinned thickness on the side where the potential difference is low.

摘要翻译： 本发明的放电灯点亮装置用高压发生变压器包括杆状铁芯， 次级卷绕筒管，其分为多个部分，其中芯部设置在其中心部分; 卷绕在次级绕线筒上的次级绕组部分，分布在线轴的多个部分之间; 设置在次级绕组部的外周的初级绕线筒管; 和卷绕在初级绕线筒上的初级绕组部分; 其中，所述初级绕线筒管的厚度在所述第二绕组部分的每个部分或多个部分中变化，使得所述线轴在所述初级绕组部分和所述次级绕组部分之间的电位差高的一侧具有增厚的厚度;以及 线轴在电位差低的一侧具有减薄的厚度。

公开(公告)号：US20080251830A1

公开(公告)日：2008-10-16

申请号：US12060522

申请日：2008-04-01

申请人： Tomoki Higashi ,  Takashi Ohsawa ,  Ryo Fukuda

发明人： Tomoki Higashi ,  Takashi Ohsawa ,  Ryo Fukuda

IPC分类号： H01L27/102 ,  G11C16/04

CPC分类号： H01L27/1022 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C11/4085 ,  G11C2211/4016 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.

摘要翻译： 本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

公开(公告)号：US07425746B2

公开(公告)日：2008-09-16

申请号：US11339469

申请日：2006-01-26

申请人： Takashi Ohsawa

发明人： Takashi Ohsawa

IPC分类号： H01L29/76

CPC分类号： H01L27/1203

摘要： A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.

摘要翻译： 根据本发明的半导体存储装置，包括：通过掩埋绝缘层在基板上形成的第一半导体层; 具有形成在第一半导体层上的浮动通道体的FBC（浮体体池），在通道体的第一面侧形成通道的主栅极和形成为在第二面上电容耦合的辅助栅极 在第一面的相对侧; 形成在第一半导体层上的逻辑电路，其通过绝缘膜与FBC分开，该绝缘膜传送用于FBC的信号; 位于FBC下方并沿着掩埋绝缘膜的下表面形成的第二半导体层; 以及第三半导体层，其位于所述逻辑电路的下方并且沿着所述掩埋绝缘膜的下表面形成，其中所述第二和第三半导体层被设定为彼此不同的电位。

公开(公告)号：US20070223272A1

公开(公告)日：2007-09-27

申请号：US11673750

申请日：2007-02-12

申请人： Takashi OHSAWA

发明人： Takashi OHSAWA

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/12 ,  G11C7/14 ,  G11C11/404 ,  G11C11/4094 ,  G11C11/4099 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2211/4016

摘要： This disclosure concerns a memory including a memory cell including a floating body in an electrically floating state and storing data according to the number of majority carriers in the floating body; a word line connected to a gate of the memory cell; a first bit line connected to the memory cell to transmit the data; a second bit line transmitting reference data used to detect the data stored in the memory cell; a first sense node and a second sense node transmitting the data stored in the memory cell and the reference data, respectively; a first short-circuiting switch provided between the first sense node and the second sense node; and a first flip-flop applying a load current to the memory cell during a data read operation and amplifying a potential difference generated between the first sense node and the second sense node by turning off the first short-circuiting switch

摘要翻译： 本公开涉及一种存储器，包括：存储单元，其包括处于浮动状态的浮动体，并且根据浮体中的多数载体的数量存储数据; 连接到存储单元的门的字线; 连接到所述存储器单元以传送所述数据的第一位线; 发送用于检测存储在存储单元中的数据的参考数据的第二位线; 第一感测节点和第二感测节点分别发送存储在存储器单元中的数据和参考数据; 设置在第一感测节点和第二感测节点之间的第一短路开关; 以及第一触发器，其在数据读取操作期间向存储器单元施加负载电流，并且通过关闭第一短路开关来放大在第一感测节点和第二感测节点之间产生的电位差

公开(公告)号：US07269084B2

公开(公告)日：2007-09-11

申请号：US11056243

申请日：2005-02-14

申请人： Kosuke Hatsuda ,  Takashi Ohsawa ,  Katsuyuki Fujita

发明人： Kosuke Hatsuda ,  Takashi Ohsawa ,  Katsuyuki Fujita

IPC分类号： G11C7/02

CPC分类号： G11C7/14 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2211/4016

摘要： The disclosure concerns a semiconductor memory device that includes memory cells that store data by accumulating or discharging an electric charge; memory cell arrays having a plurality of the memory cells disposed in a matrix; a plurality of word lines connected to the memory cells arrayed in rows of the memory cell arrays; a plurality of bit lines connected to the memory cells arrayed in columns of the memory cell arrays; a plurality of dummy cells arrayed in a row direction of the memory cell arrays and are connected to the bit lines; sense amplifiers detecting data within the memory cells by using an average value of electric characteristics of the dummy cells that store mutually different digital data as a reference signal; and a plurality of switching elements electrically connecting four or more of the bit lines in order to generate the reference signal.

摘要翻译： 本公开涉及一种半导体存储器件，其包括通过累积或放电来存储数据的存储器单元; 具有设置在矩阵中的多个存储单元的存储单元阵列; 连接到排列在存储单元阵列中的存储单元的多个字线; 多个位线连接到存储单元阵列的列中排列的存储单元; 多个虚拟单元排列在存储单元阵列的行方向上并连接到位线; 读出放大器通过使用存储相互不同的数字数据的虚拟单元的电特性的平均值作为参考信号来检测存储单元内的数据; 以及电连接四个或更多个位线以便产生参考信号的多个开关元件。