公开(公告)号：US20080056031A1

公开(公告)日：2008-03-06

申请号：US11907442

申请日：2007-10-12

Applicant: Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

Inventor： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

IPC: G11C11/4074 ,  G11C11/4063 ,  G11C7/00

CPC classification number: G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227 ,  H03K5/133

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract translation: 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。

公开(公告)号：US20070280025A1

公开(公告)日：2007-12-06

申请号：US11882230

申请日：2007-07-31

Applicant: Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

Inventor： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

IPC: G11C5/14

CPC classification number: G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227 ,  H03K5/133

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract translation: 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。

公开(公告)号：US20070223297A1

公开(公告)日：2007-09-27

申请号：US11723830

申请日：2007-03-22

Applicant: Takuya Hirota ,  Takao Yanagida

Inventor： Takuya Hirota ,  Takao Yanagida

IPC: G11C7/00 ,  G11C7/02

CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

Abstract: A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

Abstract translation: 一种半导体存储装置具有包括存储数据的多个存储单元的第一和第二单元阵列，选择性地与第一和第二单元阵列中的任一个连接的读出放大器，第一预充电电路，用于在第一和第二单元阵列中设置一对位线 单元阵列到预定电压，第二预充电电路，用于将第二单元阵列中的一对位线设置为预定电压;第一开关电路，用于将读出放大器与第一单元阵列连接;第二开关电路， 具有第二单元阵列的读出放大器和用于控制第一和第二开关电路的导通状态的开关控制器。 在非选择状态，其中读出放大器不访问任何单元阵列，开关控制器将开关电路之一控制为导通状态。

公开(公告)号：US07203113B2

公开(公告)日：2007-04-10

申请号：US11090151

申请日：2005-03-28

Applicant: Hiroyuki Takahashi ,  Takato Shimoyama ,  Takuya Hirota

Inventor： Hiroyuki Takahashi ,  Takato Shimoyama ,  Takuya Hirota

IPC: G11C7/00

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C2211/4067

Abstract: Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.

Abstract translation: 公开了一种半导体存储装置，其中以这样的方式执行控制，即如果当芯片选择信号从不活动（待机）状态转换到活动状态时不执行刷新操作，则读取或写入访问是 立即执行，并且当芯片选择信号经历从非活动状态转换到活动状态时刷新操作正在进行时，等待发生电路产生用于使读或写访问等待的等待信号。

公开(公告)号：US20060198226A1

公开(公告)日：2006-09-07

申请号：US11360593

申请日：2006-02-24

Applicant: Hiroyuki Takahashi ,  Takuya Hirota

Inventor： Hiroyuki Takahashi ,  Takuya Hirota

IPC: G11C7/00

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

Abstract: A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.

Abstract translation: 根据本发明实施例的半导体存储装置包括：多个字线; 与所述多个字线对应的多个存储单元; 以及刷新电路，用于根据定时器周期顺序驱动多个字线以刷新每个多个存储单元，该定时器周期根据从活动模式转换到活动模式时的活动模式中的干扰量来设置定时器周期 待机模式。

公开(公告)号：US07054223B2

公开(公告)日：2006-05-30

申请号：US10920249

申请日：2004-08-18

Applicant: Hiroyuki Takahashi ,  Takuya Hirota

Inventor： Hiroyuki Takahashi ,  Takuya Hirota

IPC: G11C8/00

CPC classification number: G11C11/40603 ,  G11C8/18 ,  G11C11/406

Abstract: A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.

Abstract translation: 适于避免用于刷新的字线的选择周期与用于读/写的字线的选择周期之间的冲突的半导体存储器件包括包括需要刷新以保持存储的多个存储器单元的单元阵列 用于执行控制的数据和装置，使得当在执行刷新操作的时钟周期之后的时钟周期中输入读/写请求时，单元阵列中的读/写操作被延迟至少一个时钟周期，并且 读/写操作在完成刷新后开始。

公开(公告)号：US20050105380A1

公开(公告)日：2005-05-19

申请号：US10985876

申请日：2004-11-12

Applicant: Hiroyuki Takahashi ,  Takato Shimoyama ,  Takuya Hirota

Inventor： Hiroyuki Takahashi ,  Takato Shimoyama ,  Takuya Hirota

IPC: G11C11/407 ,  G11C5/06 ,  G11C8/00

CPC classification number: G11C5/066

Abstract: A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.

Abstract translation: 半导体存储器件具有用于接收地址信号的n位的一部分或所有地址端之间的公共端子，以及用于输出其位宽为n位或更少的数据信号的数据端，以及用于接收m位的专用地址端 地址信号，其中在读取时，在输入了地址信号的n位之后，通过地址信号输入的m位，通过公共端连续地读出选定页内的多个数据信号 从专用地址终端。

公开(公告)号：US20050047239A1

公开(公告)日：2005-03-03

申请号：US10500400

申请日：2002-12-25

Applicant: Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

Inventor： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

IPC: G11C11/403 ,  G11C11/406 ,  G11C7/00

CPC classification number: G11C11/40603 ,  G11C11/406

Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

Abstract translation: 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。此后， 当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变成“H”电平，刷新请求被输入到 输出刷新脉冲发生器电路170和刷新使能信号RERF。

公开(公告)号：US06603692B2

公开(公告)日：2003-08-05

申请号：US09880469

申请日：2001-06-13

Applicant: Takuya Hirota

Inventor： Takuya Hirota

IPC: G11C700

CPC classification number: G11C8/08

Abstract: A semiconductor memory device, capable of being accessed at a high speed, according to the present invention, is provided, and is configured with the changeover point in time between the pre-charge operation and a word line selection operation on the far-end side of the sense amplifier being earlier than that on the near-end side of it. There are provided word selection signal input buffer, block selection signal input buffer, digit selection signal input buffer on semiconductor chip, decoders, which decode the said signals, drivers for the output signal of each decoder, memory block, which is stored with information, and gate circuit, which selects a column of memory cells in a memory block. Drivers for the word selection signal and block selection signal are laid out in the middle of chip and near far-end side pre-charge unit, which is located the farthest from the sense amplifier (which is deployed in near-end side pre-charge unit.

Abstract translation: 本发明提供一种能够高速访问的半导体存储器件，并且具有在远端侧的预充电动作与字线选择动作之间的时刻切换点 的感测放大器比其近端侧的读出放大器更早。 提供字选择信号输入缓冲器，块选择信号输入缓冲器，半导体芯片上的数字选择信号输入缓冲器，解码所述信号的解码器，用于每个解码器的输出信号的驱动器，存储有信息的存储器块， 和门电路，其选择存储器块中的一列存储器单元。 字选择信号和块选择信号的驱动器布置在芯片的中间和靠近远端侧的预充电单元，其位于离读出放大器最远的位置（其部署在近端侧预充电 单元。

公开(公告)号：US06262613B1

公开(公告)日：2001-07-17

申请号：US09288786

申请日：1999-04-09

Applicant: Takuya Hirota

Inventor： Takuya Hirota

IPC: H03K3017

CPC classification number: H03K5/1565 ,  H03K5/04

Abstract: A pulse duration changer generates an output pulse signal longer in pulse duration than an input pulse signal, wherein the pulse duration changer firstly produces a first control pulse signal synchronous with the input pulse signal and shorter in pulse duration than the input pulse signal, thereafter, produces a second control pulse signal synchronous with the first control pulse signal and longer in pulse duration than the input pulse signal, and finally defines the pulse duration of a preliminary output pulse signal as long as the second control pulse signal, thereby keeping the pulse duration of the output signal constant when the input pulse signal has an ultra high frequency.

Abstract translation: 脉冲持续时间变换器产生脉冲持续时间比输入脉冲信号更长的输出脉冲信号，其中脉冲持续时间改变器首先产生与输入脉冲信号同步的第一控制脉冲信号并且脉冲持续时间比输入脉冲信号更短， 产生与第一控制脉冲信号同步的第二控制脉冲信号，并且脉冲持续时间比输入脉冲信号长，并且最终定义初步输出脉冲信号的脉冲持续时间，只要该第二控制脉冲信号，从而保持脉冲持续时间 当输入脉冲信号具有超高频时，输出信号恒定。