公开(公告)号：US20070026681A1

公开(公告)日：2007-02-01

申请号：US10568960

申请日：2004-08-26

申请人： Toshiaki Shiraiwa ,  Tetsuya Tatsumi ,  Seiji Samukawa

发明人： Toshiaki Shiraiwa ,  Tetsuya Tatsumi ,  Seiji Samukawa

IPC分类号： H01L21/302

CPC分类号： H01L21/32136 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/12

摘要： Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction.

摘要翻译： 提供一种能够优选刻蚀特别是用于MRAM的引脚层的PtMn的工艺是一种目标：通过使用脉冲等离子体对包括铂和/或锰的层进行干蚀刻的干式蚀刻方法和MRAM的制造方法 其中干蚀刻方法适用于针层的处理。 MRAM被配置为具有包括由通过堆叠具有固定磁化方向的磁性固定层，隧道势垒层和能够改变磁化方向的磁性层形成的隧道磁阻效应元件组成的磁存储元件的存储部分。

公开(公告)号：US20050247672A1

公开(公告)日：2005-11-10

申请号：US11110380

申请日：2005-04-20

申请人： Tetsuya Tatsumi

发明人： Tetsuya Tatsumi

IPC分类号： H01L21/3065 ,  C23F1/00 ,  H01L21/302 ,  H01L21/311

CPC分类号： H01L21/31116

摘要： A method for plasma etching an insulating layer by using a fluorocarbon etching gas, the method including controlling the sheath potential Vs (or ion accelerating voltage) that appears on the outermost surface of the plasma surrounding parts of the plasma etching equipment in response to the value (Fc) of F0/C0, where C0 and F0 each denote the total amount of carbon atoms and fluorine atoms constituting the fluorocarbon etching gas, so as to avoid deposition of residues on the plasma surrounding parts. This method permits stable plasma etching.

摘要翻译： 一种通过使用碳氟化合物蚀刻气体等离子体蚀刻绝缘层的方法，该方法包括控制出现在等离子体周围部分的最外表面上的鞘电位V S（或离子加速电压） 等离子体蚀刻设备，其响应于F 0 0 / C 0 0的值（Fc），其中C 0和/或0 < SUB>各自表示构成碳氟化合物蚀刻气体的碳原子和氟原子的总量，以避免残留在等离子体周围部分上的沉积。 该方法允许稳定的等离子体蚀刻。

公开(公告)号：US5660681A

公开(公告)日：1997-08-26

申请号：US699079

申请日：1996-08-19

申请人： Seiichi Fukuda ,  Tetsuya Tatsumi

发明人： Seiichi Fukuda ,  Tetsuya Tatsumi

IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3213

CPC分类号： H01L21/02071 ,  H01L21/32137 ,  Y10S438/963

摘要： A method for processing a layer of a silicon-based material on a wafer by which a sidewall protective film may be removed sufficiently and efficiently. An etching gas capable of yielding chlorine- or bromine-based chemical species and oxygen-based chemical species is used for dry etching a polycide film formed on a gate insulating film, plasma processing with an oxygen-based gas is then carried out for ashing the resist mask and removing carbonaceous components in the sidewall protective film. In addition, the sidewall protective film is oxidized so that the composition to that of stoichiometrically stable SiO.sub.2 is approached. Subsequently, the modified sidewall protective film is removed by processing with a dilute hydrofluoric acid solution. Since this sufficiently removes the sidewall protective film, it becomes possible to reduce the amount of dust and to improve coverage of a film to be formed by the next step. In this manner, a semiconductor device may be prepared with improved reliability and production yield.

摘要翻译： 一种在晶片上处理硅基材料层的方法，通过该方法可以充分有效地去除侧壁保护膜。 使用能够产生基于氯或溴的化学物质和氧基化学物质的蚀刻气体用于干蚀刻形成在栅极绝缘膜上的多晶硅膜，然后进行用氧基气体的等离子体处理以灰化 防止掩模和去除侧壁保护膜中的碳质成分。 此外，侧壁保护膜被氧化，使得组成与化学计量稳定的SiO 2的组成接近。 随后，用稀氢氟酸溶液处理除去改性侧壁保护膜。 由于这充分地除去了侧壁保护膜，所以可以减少灰尘的量并提高通过下一步骤形成的膜的覆盖率。 以这种方式，可以制备具有改善的可靠性和产量的半导体器件。

公开(公告)号：US20080286883A1

公开(公告)日：2008-11-20

申请号：US12153848

申请日：2008-05-27

申请人： Toshiaki Shiraiwa ,  Tetsuya Tatsumi ,  Seiji Samukawa

发明人： Toshiaki Shiraiwa ,  Tetsuya Tatsumi ,  Seiji Samukawa

IPC分类号： H01L21/04

CPC分类号： H01L21/32136 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/12

摘要： Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction.

摘要翻译： 提供一种能够优选刻蚀特别是用于MRAM的引脚层的PtMn的工艺是一种目标：通过使用脉冲等离子体对包括铂和/或锰的层进行干蚀刻的干式蚀刻方法和MRAM的制造方法 其中干蚀刻方法适用于针层的处理。 MRAM被配置为具有包括由通过堆叠具有固定磁化方向的磁性固定层，隧道势垒层和能够改变磁化方向的磁性层形成的隧道磁阻效应元件组成的磁存储元件的存储部分。

公开(公告)号：US20070298615A1

公开(公告)日：2007-12-27

申请号：US11668679

申请日：2007-01-30

申请人： Nobuyuki Matsuzawa ,  Atsuhiro Ando ,  Eriko Matsui ,  Yuko Yamaguchi ,  Katsuhisa Kugimiya ,  Tetsuya Tatsumi ,  Salam Kazi ,  Takeshi Iwai ,  Makiko Irie

发明人： Nobuyuki Matsuzawa ,  Atsuhiro Ando ,  Eriko Matsui ,  Yuko Yamaguchi ,  Katsuhisa Kugimiya ,  Tetsuya Tatsumi ,  Salam Kazi ,  Takeshi Iwai ,  Makiko Irie

IPC分类号： H01L21/311

CPC分类号： H01L21/0273 ,  G03F7/40 ,  H01L21/28123 ,  H01L21/32139

摘要： A pattern forming method is provided. The pattern forming method includes a first step of forming a resist pattern including a lactone group-containing skeleton above an etched layer provided on a substrate; a second step of performing plasma processing using a hydrogen-containing gas to lower a glass transition temperature or a softening point of the resist pattern; and a third step of transferring the resist pattern after the plasma processing to the etched layer by etching, and forming the pattern of the etched layer.

摘要翻译： 提供了图案形成方法。 图案形成方法包括：在设置在基板上的蚀刻层的上方形成含有含内酯基的骨架的抗蚀剂图案的第一工序; 使用含氢气体进行等离子体处理以降低玻璃化转变温度或抗蚀剂图案的软化点的第二步骤; 以及通过蚀刻将等离子体处理后的抗蚀剂图案转印到蚀刻层的第三步骤，以及形成蚀刻层的图案。

公开(公告)号：US20050019962A1

公开(公告)日：2005-01-27

申请号：US10877391

申请日：2004-06-25

申请人： Tetsuya Tatsumi

发明人： Tetsuya Tatsumi

IPC分类号： H01L21/3065 ,  G03F7/42 ,  H01L21/00 ,  H01L21/027 ,  H01L21/28 ,  H01L21/311 ,  H05H1/02

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01J37/32935 ,  H01L21/0271 ,  H01L21/28202 ,  Y10T436/12

摘要： Disclosed is a plasma monitoring method for detecting the amount of atomic radicals generated by dissociation of a molecular raw material gas during a plasma processing conducted by introducing the molecular raw material gas and a rare gas into a process atmosphere, wherein the amount of the atomic radicals is predicted from the dissociation degree of the molecular raw material gas determined from the partial pressure of the molecular raw material gas in the process atmosphere, the luminous intensity of the rare gas, and the partial pressure of the rare gas in the process atmosphere, whereby the amount of the specific atomic radicals can be monitored easily and accurately.

摘要翻译： 公开了一种等离子体监测方法，用于检测在通过将分子原料气体和稀有气体引入到处理气氛中进行的等离子体处理期间分子原料气体的解离产生的原子自由基的量，其中原子团的量 由处理气氛中的分子原料气体的分压，稀有气体的发光强度和处理气氛中的稀有气体的分压确定的分子原料气体的离解度进行预测，由此 可以容易且准确地监测特定原子团的量。

公开(公告)号：US5368686A

公开(公告)日：1994-11-29

申请号：US899181

申请日：1992-06-16

申请人： Tetsuya Tatsumi ,  Tetsuji Nagayama

发明人： Tetsuya Tatsumi ,  Tetsuji Nagayama

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L21/00

CPC分类号： H01L21/32137 ,  Y10S438/963

摘要： A dry etching method for anisotropically etching a polycide film without using chlorofluorocarbon (CFC). For instance, in a W polycide gate electrode forming process, a W polycide film is etched by using sulfur fluorides, like S.sub.2 F.sub.2, with a high S/F ratio (i.e. the ratio of the number of sulfur atoms to that of fluorine atoms). In a first step, at least the upper WSi.sub.x layer of the W polycide film is etched with the wafer kept at temperatures between -20.degree. C. and room temperature or with non-depositional fluorine based compounds like SF.sub.6 added to etching gas, thus decreasing the S/F ratio of the etching system. This first step promotes elimination of WF.sub.x and reduces the quantity of free sulfur. Therefore, WF.sub.x is inhibited from reacting with sulfur to form WS.sub.x for deposition in excessive quantities on the sidewalls of the WSi.sub.x pattern, thus preventing occurrence of critical dimension losses between the resist mask and the W polycide gate electrode. In a second step, the lower polysilicon layer of the W polycide film is etched with the wafer cooled to lower temperatures or with H.sub.2 S, etc. added to etching gas, thus increasing the S/F ratio of the etching system. This second step promotes deposition of sulfur on the sidewalls of the polycide pattern and improves anisotropy.

摘要翻译： 不使用氯氟烃（CFC）的各向异性蚀刻多硅化物膜的干式蚀刻方法。 例如，在W多晶硅栅极电极形成工序中，通过使用硫化氢（如S2F2），以高S / F比（即硫原子数与氟原子的比例）来蚀刻W多晶硅化合物膜。 在第一步骤中，至少W多硅化物膜的上WSix层被蚀刻，晶片保持在-20℃至室温之间，或者与添加到蚀刻气体中的非沉积氟基化合物如SF 6一起蚀刻，因此减小 蚀刻系统的S / F比。 这第一步促进消除WFx并减少游离硫的量。 因此，WFx被抑制与硫反应以形成WSx以在WSix图案的侧壁上过量沉积，从而防止在抗蚀剂掩模和W多选择栅电极之间出现临界尺寸损失。 在第二步骤中，通过将晶片冷却至较低温度或将H 2 S等添加到蚀刻气体中来蚀刻W多晶硅膜的下部多晶硅层，从而提高蚀刻系统的S / F比。 该第二步骤促进了硫在多晶硅化物图案的侧壁上的沉积，并改善了各向异性。

公开(公告)号：US5200028A

公开(公告)日：1993-04-06

申请号：US741735

申请日：1991-08-07

申请人： Tetsuya Tatsumi

发明人： Tetsuya Tatsumi

IPC分类号： H01L21/302 ,  C23F4/00 ,  H01L21/3065 ,  H01L21/3213

CPC分类号： H01L21/32137

摘要： A process is disclosed for etching a silicon-based structure comprised of a silicon layer and a high-melting silicide layer. Good shaping results from etching of the two layers with use of two gaseous mixtures having their respective different ratios of a hydrogen bromide gas and a fluorine radical-donating gas. Separate etching is possible of the silicon layer with a hydrogen bromide gas and of the silicide layer with a gaseous mixture of the above type. A silicon-containing layer is also etched with a hydrogen gas alone with the end point of etching being precisely detected.

摘要翻译： 公开了用于蚀刻由硅层和高熔点硅化物层组成的硅基结构的方法。 通过使用两种具有各自不同比例的溴化氢气体和氟自由基供体气体的气体混合物来蚀刻两层，导致良好的成型。 可以使用溴化氢气体和硅化物层与上述类型的气体混合物进行单独蚀刻。 仅用氢气蚀刻含硅层，并精确地检测蚀刻的终点。

公开(公告)号：US10998174B2

公开(公告)日：2021-05-04

申请号：US12332119

申请日：2008-12-10

申请人： Nobuyuki Kuboi ,  Tetsuya Tatsumi

发明人： Nobuyuki Kuboi ,  Tetsuya Tatsumi

IPC分类号： H01L21/02 ,  H01L21/3065 ,  H01J37/32

摘要： A dry etching equipment includes a topography simulator and a control section. The topography simulator controls an amount of deposition species incident upon a sidewall to be processed in accordance with a wafer opening ratio and a solid angle of a local pattern, the deposition amount being represented by a product of a reaction product flux and the solid angle. The control section compares a database obtained by the topography simulator with an actual measured value detected from an etching condition during dry etching to calculate a correction value for etching process, and indicates the correction value to an etching chamber in the dry etching equipment. The dry etching equipment corrects in real time a parameter for the etching process conducted in the etching chamber.

公开(公告)号：US08649893B2

公开(公告)日：2014-02-11

申请号：US12962816

申请日：2010-12-08

申请人： Nobuyuki Kuboi ,  Tetsuya Tatsumi

发明人： Nobuyuki Kuboi ,  Tetsuya Tatsumi

IPC分类号： G06F19/00

CPC分类号： H01L21/67253 ,  H01J37/32522 ,  H01J37/32935 ,  H01J37/32972 ,  H01L21/31116

摘要： Disclosed herein is a semiconductor manufacturing device including, a chamber, a sensor, a sticking probability calculating section, an acting section, and a control section.

摘要翻译： 这里公开了一种半导体制造装置，包括室，传感器，粘附概率计算部，作用部和控制部。