公开(公告)号：US20250056818A1

公开(公告)日：2025-02-13

申请号：US18367467

申请日：2023-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a bottom portion, a middle portion, a top portion, and a base portion between the bottom portion and the substrate. Preferably, the bottom portion is surrounded by a shallow trench isolation (STI), a gate oxide layer is disposed on the fin-shaped structure and the STI, a bottom surface of the gate oxide layer is higher than a top surface of the base portion, a width of a top surface of the bottom portion is greater than half the width of the bottom surface of the bottom portion, and a tip of the top portion includes a tapered portion.

公开(公告)号：US12224001B2

公开(公告)日：2025-02-11

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

公开(公告)号：US20250048936A1

公开(公告)日：2025-02-06

申请号：US18919382

申请日：2024-10-17

Applicant: United Microelectronics Corp.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

公开(公告)号：US20250040195A1

公开(公告)日：2025-01-30

申请号：US18917979

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer and including a device region, and a charge trap layer in the substrate and extending between the insulating layer and the substrate and directly under the device region. The charge trap layer includes a plurality of n-type first doped regions and a plurality of p-type second doped regions alternately arranged and directly in contact with each other to form a plurality of interrupted depletion junctions.

公开(公告)号：US20250040180A1

公开(公告)日：2025-01-30

申请号：US18916695

申请日：2024-10-15

Applicant: United Microelectronics Corp.

Inventor： Zong-Han Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: A lateral diffused metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a second fin-shaped structure adjacent to the first fin-shaped structure, a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, a first gate structure on the first fin-shaped structure and part of the STI, a second gate structure on the second fin-shaped structure, and an air gap between the first gate structure and the second gate structure.

公开(公告)号：US20250040149A1

公开(公告)日：2025-01-30

申请号：US18916730

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

公开(公告)号：US12211888B2

公开(公告)日：2025-01-28

申请号：US17160319

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chi-Mao Hsu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Hsin-Fu Huang

IPC: H01C17/08 ,  H01C7/00 ,  H01L49/02

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

公开(公告)号：US12205909B2

公开(公告)日：2025-01-21

申请号：US18138752

申请日：2023-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

公开(公告)号：US20250017121A1

公开(公告)日：2025-01-09

申请号：US18449716

申请日：2023-08-15

Applicant: United Microelectronics Corp.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang

IPC: H10N70/00 ,  H10B63/00

Abstract: A resistive memory structure including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer is provided. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion portion located outside the dielectric layer. The resistive memory device is located on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacer is located on a sidewall of the resistive memory device. The protective layer is located on a sidewall of the protrusion portion and between the first electrode and the dielectric layer.

公开(公告)号：US20250015186A1

公开(公告)日：2025-01-09

申请号：US18227299

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chun Lee ,  Chih-Yi Wang ,  Wei-Che Chen ,  Ya-Ting Hu ,  Yao-Jhan Wang ,  Kun-Szu Tseng ,  Feng-Yun Cheng ,  Shyan-Liang Chou

IPC: H01L29/78 ,  H01L25/16

Abstract: The invention provides a semiconductor structure, which comprises a middle/high voltage device region and a low voltage device region, a plurality of fin structures disposed in the low voltage device region, and a protruding part located at a boundary Between the middle/high voltage device region and the low voltage device region. A top surface of the protruding part is flat, and the top surface of the protruding part is aligned with a flat top surface of the middle/high voltage device region.