公开(公告)号：US20140153620A1

公开(公告)日：2014-06-05

申请号：US13739782

申请日：2013-01-11

Applicant: Lorenzo Longo ,  Vivek Telang

Inventor： Lorenzo Longo ,  Vivek Telang

IPC: H04L25/49

CPC classification number: H04L25/4917 ,  H04L25/03057 ,  H04L25/03885 ,  H04L27/02

Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.

Abstract translation: 短距离通信系统包括多个通信SERDES，其通过短距离信道介质传送数据，例如位于公共PCB上的码片之间的背板连接（例如，PCB轨迹）。 生成多级调制数据信号以通过短距离信道介质发送/接收数据。 诸如四电平PAM的多电平调制数据信号降低数据信号速率，从而降低插入损耗，功率，电路的复杂性以及所需的芯片空间。

公开(公告)号：US07525470B2

公开(公告)日：2009-04-28

申请号：US11845765

申请日：2007-08-27

Applicant: Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

Inventor： Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

IPC: H03M1/12

CPC classification number: H03M1/0836 ,  H03M1/1215 ,  H03M1/183

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract translation: 实施例包括一种用于对通过通信信道接收的电磁信号进行色散补偿的系统，该电磁信号以符号速率承载信息。 可以使用交错模数转换器（“ADC”）块，其中交织的ADC块可以被配置为从电磁信号生成多个数字采样的信号。 交织的均衡器块可以被配置为数字地处理由ADC块产生的数字采样信号中的每一个以产生多个数字均衡的信号。 多路复用器可以被配置为将数字均衡的信号聚合成复合输出信号。

公开(公告)号：US20080049847A1

公开(公告)日：2008-02-28

申请号：US11837278

申请日：2007-08-10

Applicant: Vivek Telang ,  Vasudevan Parthasarathy ,  Sudeep Bhoja ,  Hong Chen ,  Afshin Momtaz ,  Chung-Jue Chen ,  Ali Ghiasi ,  Michael Furlong ,  Lorenzo Longo

Inventor： Vivek Telang ,  Vasudevan Parthasarathy ,  Sudeep Bhoja ,  Hong Chen ,  Afshin Momtaz ,  Chung-Jue Chen ,  Ali Ghiasi ,  Michael Furlong ,  Lorenzo Longo

IPC: H04B14/04

CPC classification number: H04L25/03063 ,  H04B10/25133 ,  H04B10/697 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0307 ,  H04L2025/03356 ,  H04L2025/0349 ,  H04L2025/03509

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract translation: 实施例包括一种用于对通过通信信道接收的电磁信号进行色散补偿的系统，该电磁信号以符号速率承载信息。 可以使用交错模数转换器（“ADC”）块，其中交织的ADC块可以被配置为从电磁信号生成多个数字采样的信号。 交织的均衡器块可以被配置为数字地处理由ADC块产生的数字采样信号中的每一个以产生多个数字均衡的信号。 多路复用器可以被配置为将数字均衡的信号聚合成复合输出信号。

公开(公告)号：US07830987B2

公开(公告)日：2010-11-09

申请号：US11837301

申请日：2007-08-10

Applicant: Sudeep Bhoja ,  Vasudevan Parthasarathy ,  Vivek Telang

Inventor： Sudeep Bhoja ,  Vasudevan Parthasarathy ,  Vivek Telang

IPC: H04L27/14

CPC classification number: H04L7/0062

Abstract: Embodiments include a system for performing electronic dispersion compensation on an information-bearing signal transmitted over a communication channel. The system may include a channel identification module configured to receive a first digitized version of the information bearing signal and an equalized version of the information-bearing signal, and may be configured to determine an impulse response of the communication channel based thereon. The system may include a time varying phase detector configured to receive the equalized version of the information bearing signal, a second digitized version of the information-bearing signal, and the impulse response, and may be further configured to generate a reference wave based on the impulse response and the equalized version of the information-bearing signal. The time varying phase detector may be configured to generate a phase signal based on the reference wave and on an error signal determined from the reference wave and the second digitized version of the information-bearing signal.

Abstract translation: 实施例包括用于对通过通信信道发送的信息承载信号执行电子色散补偿的系统。 系统可以包括信道识别模块，其被配置为接收信息承载信号的第一数字化版本和信息承载信号的均衡版本，并且可以被配置为基于该信道识别模块来确定通信信道的脉冲响应。 系统可以包括时变相位检测器，其被配置为接收信息承载信号的均衡版本，信息承载信号的第二数字化版本和脉冲​​响应，并且还可以被配置为基于 脉冲响应和信息承载信号的均衡版本。 时变相位检测器可以被配置为基于参考波和从信息承载信号的参考波和第二数字化版本确定的误差信号来生成相位信号。

公开(公告)号：US08913706B2

公开(公告)日：2014-12-16

申请号：US12860596

申请日：2010-08-20

Applicant: Jun Cao ,  Afshin Momtaz ,  Chung-Jue Chen ,  Kang Xiao ,  Vivek Telang ,  Ali Ghiasi

Inventor： Jun Cao ,  Afshin Momtaz ,  Chung-Jue Chen ,  Kang Xiao ,  Vivek Telang ,  Ali Ghiasi

IPC: H03D3/24

CPC classification number: H03L7/18

Abstract: A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider.

Abstract translation: 一种用于从单个恒定输入参考时钟频率产生多个输出时钟频率之一的电路。 该电路包括参考时钟系统和锁相环。 参考时钟系统包括旁路路径，包括第一整数除法器的分频器路径和多路复用器。 第一整数分频器的除数基于一组可能的通信协议的所选通信协议。 多路复用器被配置为基于所选择的通信协议来路由旁路路径或分路器路径。 锁相环包括压控振荡器和反馈路径。 反馈路径包括第二整数分频器。 第二整数分频器的除数基于所选择的通信协议。 参考时钟系统被配​​置为接收恒定的参考时钟频率。 压控振荡器被配置为产生与所选择的通信协议相对应的多个输出时钟频率中的一个。 所选择的输出时钟频率基于多路复用器的路由，第一整数除法器的除数和第二整数除法器的除数中的至少一个来产生。

公开(公告)号：US08442159B2

公开(公告)日：2013-05-14

申请号：US12883842

申请日：2010-09-16

Applicant: Vivek Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

Inventor： Vivek Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

IPC: H04L27/06 ,  H03D1/00

CPC classification number: H04L27/0002 ,  H04B1/0007 ,  H04B1/406

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

公开(公告)号：US08428111B2

公开(公告)日：2013-04-23

申请号：US11799368

申请日：2007-05-01

Applicant: Magesh Valliappan ,  Howard Baumer ,  Anthony Brewster ,  Vivek Telang

Inventor： Magesh Valliappan ,  Howard Baumer ,  Anthony Brewster ,  Vivek Telang

IPC: H03H7/30 ,  H03K5/159

CPC classification number: H04L25/03343 ,  H04B3/143 ,  H04B3/32 ,  H04L25/03038

Abstract: Various embodiments are disclosed relating to crosstalk emission management. In an example embodiment, an amplitude of a main tap of a transmit equalizer may be determined to limit crosstalk emitted from a local channel to one or more other channels to be less than a threshold. A ratio of an amplitude of at least one secondary tap of the transmit equalizer to the amplitude of the main tap may be determined to provide equalization to the local channel.

Abstract translation: 公开了与串扰发射管理相关的各种实施例。 在示例性实施例中，可以确定发射均衡器的主抽头的幅度以将从本地信道发射到一个或多个其他信道的串扰限制为小于阈值。 可以确定发射均衡器的至少一个次级抽头的幅度与主抽头的幅度的比率，以向本地信道提供均衡。

公开(公告)号：US08369453B2

公开(公告)日：2013-02-05

申请号：US12314051

申请日：2008-12-03

Applicant: Namik Kemal Kocaman ,  Afshin Momtaz ,  Velu Chellam Pillai ,  Vivek Telang ,  Sundararajan Chidambara ,  Magesh Valliappan

Inventor： Namik Kemal Kocaman ,  Afshin Momtaz ,  Velu Chellam Pillai ,  Vivek Telang ,  Sundararajan Chidambara ,  Magesh Valliappan

IPC: H03K9/00

CPC classification number: H04B17/21 ,  H03F3/195 ,  H03F2200/375 ,  H03F2200/405 ,  H04L25/03019 ,  H04L27/08

Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.

公开(公告)号：US20120007640A1

公开(公告)日：2012-01-12

申请号：US12860596

申请日：2010-08-20

Applicant: Jun CAO ,  Afshin MOMTAZ ,  Chung-Jue CHEN ,  Kang XIAO ,  Vivek TELANG ,  Ali GHIASI

Inventor： Jun CAO ,  Afshin MOMTAZ ,  Chung-Jue CHEN ,  Kang XIAO ,  Vivek TELANG ,  Ali GHIASI

IPC: H03L7/06 ,  H03L7/08

CPC classification number: H03L7/18

Abstract: A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider.

Abstract translation: 一种用于从单个恒定输入参考时钟频率产生多个输出时钟频率之一的电路。 该电路包括参考时钟系统和锁相环。 参考时钟系统包括旁路路径，包括第一整数除法器的分频器路径和多路复用器。 第一整数分频器的除数基于一组可能的通信协议的所选通信协议。 多路复用器被配置为基于所选择的通信协议来路由旁路路径或分路器路径。 锁相环包括压控振荡器和反馈路径。 反馈路径包括第二整数分频器。 第二整数分频器的除数基于所选择的通信协议。 参考时钟系统被配​​置为接收恒定的参考时钟频率。 压控振荡器被配置为产生与所选择的通信协议相对应的多个输出时钟频率中的一个。 所选择的输出时钟频率基于多路复用器的路由，第一整数除法器的除数和第二整数除法器的除数中的至少一个来产生。

公开(公告)号：US20090232151A1

公开(公告)日：2009-09-17

申请号：US12112785

申请日：2008-04-30

Applicant: Michael Furlong ,  Vivek Telang

Inventor： Michael Furlong ,  Vivek Telang

IPC: H04L12/56

CPC classification number: H04L12/6418 ,  H04L49/90

Abstract: An apparatus is disclosed that includes first transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a first Ethernet communication protocol at a first data rate, second transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a second Ethernet communication protocol at a second data rate; and third transceiver circuitry adapted for transmitting and receiving Ethernet data over a network using a third Ethernet communication protocol at a third data rate.

Abstract translation: 公开了一种装置，其包括适于通过网络使用第一数据速率的第一以太网通信协议在网络上发送和接收以太网数据的第一收发器电路，适于通过第二以太网通信协议通过网络发送和接收以太网数据的第二收发器电路 以第二数据速率; 以及第三收发器电路，其适于以第三数据速率使用第三以太网通信协议通过网络发送和接收以太网数据。