利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.016 秒)

    System and method for characterizing process variations
    11.
    发明授权
    System and method for characterizing process variations 有权
    用于表征过程变化的系统和方法

    公开(公告)号：US08258883B2

    公开(公告)日：2012-09-04

    申请号：US12617391

    申请日：2009-11-12

    申请人： Yi-Wei Chen ,  Chi-Wei Hu ,  Wei-Pin Changchien ,  Chin-Chou Liu

    发明人： Yi-Wei Chen ,  Chi-Wei Hu ,  Wei-Pin Changchien ,  Chin-Chou Liu

    IPC分类号： H03K3/03 ,  G01R23/175 ,  G01R31/26

    CPC分类号： H03K3/0315

    摘要： A system and method for characterizing process variations are provided. A circuit comprises a plurality of inverters arranged in a sequential loop, and a plurality of transmission gates, with each transmission gate coupled between a pair of serially arranged inverters. Each transmission gate comprises a first field effect transistor (FET) having a first channel, and a second FET having a second channel. The first channel and the second channel are coupled in parallel and a gate terminal of the first FET and a gate terminal of the second FET are coupled to a first control signal and a second control signal, respectively.

    摘要翻译： 提供了一种用于表征过程变化的系统和方法。 电路包括以顺序环路布置的多个反相器，以及多个传输门，其中每个传输门耦合在一对串联布置的反相器之间。 每个传输门包括具有第一通道的第一场效应晶体管（FET）和具有第二通道的第二FET。 第一通道和第二通道并联耦合，并且第一FET的栅极端子和第二FET的栅极端子分别耦合到第一控制信号和第二控制信号。

    Method for Detecting Small Delay Defects
    13.
    发明申请
    Method for Detecting Small Delay Defects 有权
    检测小延迟缺陷的方法

    公开(公告)号：US20120112763A1

    公开(公告)日：2012-05-10

    申请号：US12943379

    申请日：2010-11-10

    申请人： Sandeep Kumar Goel ,  Saurabh Gupta ,  Wei-Pin Changchien ,  Chin-Chou Liu

    发明人： Sandeep Kumar Goel ,  Saurabh Gupta ,  Wei-Pin Changchien ,  Chin-Chou Liu

    IPC分类号： G01R23/20

    CPC分类号： G01R31/318328

    摘要： System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group.

    摘要翻译： 公开了用于有效检测小延迟缺陷的系统和方法。 该方法首先加载集成电路的布局信息。 然后，基于它们的物理信息将集成电路的网络和路径划分成两组。 物理信息包括每个路径和网络的长度以及每个路径和网络处的通道数量。 定时感知自动测试模式发生器被配置为产生具有对小延迟缺陷敏感的路径和网络的第一组的测试模式。 传统的转换延迟故障测试模式发生器被配置为产生第二组的测试模式。

    RC Delay Detectors with High Sensitivity for Through Substrate Vias
    14.
    发明申请
    RC Delay Detectors with High Sensitivity for Through Substrate Vias 有权
    具有高灵敏度的RC延迟检测器用于穿透基板通孔

    公开(公告)号：US20120038388A1

    公开(公告)日：2012-02-16

    申请号：US12971204

    申请日：2010-12-17

    申请人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Pei-Ying Lin ,  Ta-Wen Hung

    发明人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Pei-Ying Lin ,  Ta-Wen Hung

    IPC分类号： H03K19/21 ,  H03K17/00

    CPC分类号： H03K19/23 ,  G01R31/31816 ,  H03K19/17764

    摘要： A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.

    摘要翻译： 芯片包括贯穿芯片的衬底的多个贯穿衬底通孔（TSV），其中多个TSV被分组为多个TSV对。 多个接触焊盘耦合到多个TSV，其中多个接触焊盘暴露在模具的第一表面上。 芯片还包括多个平衡脉冲比较单元，其中多个平衡脉冲比较单元中的每一个包括耦合到多个TSV对之一的第一TSV和第二TSV的第一输入和第二输入。 芯片还包括多个脉冲锁存器，每个脉冲锁存器包括耦合到多个平衡脉冲比较单元之一的输出的输入端。

    System and Method for Reducing Processor Power Consumption
    15.
    发明申请
    System and Method for Reducing Processor Power Consumption 有权
    降低处理器功耗的系统和方法

    公开(公告)号：US20100174933A1

    公开(公告)日：2010-07-08

    申请号：US12619428

    申请日：2009-11-16

    申请人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Myron Shak ,  Wei-Pin Changchien ,  Kuo-Yin Chen ,  Chi Wei Hu ,  Kevin Hung ,  Wu-An Kuo

    发明人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Myron Shak ,  Wei-Pin Changchien ,  Kuo-Yin Chen ,  Chi Wei Hu ,  Kevin Hung ,  Wu-An Kuo

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

    摘要： A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.

    摘要翻译： 公开了一种用于减少处理器中的有功功率的系统和方法。 方法实施例包括以下步骤：确定特定逻辑块何时不活动，确定特定逻辑块的供电状态，将特定逻辑块与主处理器内核隔离，以及断开特定逻辑块。 当系统需要特定逻辑块时，该方法还包括重新激活该块。 系统实施例包括耦合到时钟控制模块，隔离控制模块和报头/页脚模块的软件和处理器，其可操作以隔离特定逻辑块并关闭特定逻辑块，从而降低功率。 另一个实施例包括通过时钟门控模块耦合到时钟的逻辑模块，用于隔离逻辑模块的隔离模块，用于禁止对逻辑模块供电的报头/页脚模块，以及用于控制时钟的电源和时钟门控控制模块 门控模块和页眉/页脚模块。