公开(公告)号：US20100321102A1

公开(公告)日：2010-12-23

申请号：US12486159

申请日：2009-06-17

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan

IPC分类号： G05F1/10

CPC分类号： H03K19/0013 ,  H03K19/0016

摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

摘要翻译： 在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。 电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。 功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。 功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

公开(公告)号：US08839020B2

公开(公告)日：2014-09-16

申请号：US13420800

申请日：2012-03-15

申请人： Jingcheng Zhuang ,  Nam V. Dang ,  Xiaohua Kong ,  Zhi Zhu ,  Tirdad Sowlati ,  Behnam Amelifard

发明人： Jingcheng Zhuang ,  Nam V. Dang ,  Xiaohua Kong ,  Zhi Zhu ,  Tirdad Sowlati ,  Behnam Amelifard

IPC分类号： G06F1/04 ,  G06F1/12 ,  H03L7/00 ,  H04B7/212 ,  H04L12/28 ,  H04J3/06 ,  H04L7/00 ,  H04B1/16 ,  G06F15/16

CPC分类号： H03L7/0807 ,  H03L7/087 ,  H03L7/091 ,  H03L7/14 ,  H04L7/0004 ,  H04L7/033

摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

摘要翻译： 时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。 时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。 振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。 时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。 相位检测器电路耦合到振荡器。 相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

公开(公告)号：US08742864B2

公开(公告)日：2014-06-03

申请号：US12939206

申请日：2010-11-04

申请人： Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03C3/06

CPC分类号： H03L7/1976

摘要： In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path.

摘要翻译： 在一个具体实施例中，一种方法包括基于存储的数字值来调节在锁相环电路的反馈路径上的分频器的输入，该数字值表示施加到调制器电路的基于时间的波形的一部分。 基于反馈路径的输出检索存储的数字值。

公开(公告)号：US20130120071A1

公开(公告)日：2013-05-16

申请号：US13294902

申请日：2011-11-11

申请人： Swarna L. Navubothu ,  Cheng Zhong ,  Nam V. Dang ,  Xiaohua Kong

发明人： Swarna L. Navubothu ,  Cheng Zhong ,  Nam V. Dang ,  Xiaohua Kong

IPC分类号： H03L7/00 ,  G06F17/50

CPC分类号： H03L7/0995 ,  H03K3/0315

摘要： A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning voltage. The tuning voltage range extension circuit is configured to selectively change current supplied by the first path as the tuning voltage exceeds a capacity threshold of the first transistor.

摘要翻译： 电路包括包括第一晶体管和第一电流源的第一路径。 第一晶体管响应调谐电压。 电路还包括响应于调谐电压的调谐电压范围扩展电路。 调谐电压范围扩展电路被配置为当调谐电压超过第一晶体管的容量阈值时选择性地改变由第一路径提供的电流。

公开(公告)号：US20130120036A1

公开(公告)日：2013-05-16

申请号：US13363410

申请日：2012-02-01

申请人： Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03L7/08

CPC分类号： H03L7/0802 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/0995 ,  H04L7/0276 ,  H04L7/0338

摘要： A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

公开(公告)号：US20130033329A1

公开(公告)日：2013-02-07

申请号：US13204267

申请日：2011-08-05

申请人： Zhi Zhu ,  Xiaohua Kong ,  Vannam Dang ,  Cheng Zhong

发明人： Zhi Zhu ,  Xiaohua Kong ,  Vannam Dang ,  Cheng Zhong

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03L1/00 ,  H03L2207/06

摘要： A circuit includes a controllable oscillator and a controller coupled to the controllable oscillator. The controller is configured to provide a current control and a gain control to the controllable oscillator. The gain control is configured to change a gain of the controllable oscillator during a calibration process.

摘要翻译： 电路包括可控振荡器和耦合到可控振荡器的控制器。 控制器被配置为向可控振荡器提供电流控制和增益控制。 增益控制被配置为在校准过程期间改变可控振荡器的增益。

公开(公告)号：US08798217B2

公开(公告)日：2014-08-05

申请号：US12938405

申请日：2010-11-03

申请人： Xiaohua Kong ,  Zhi Zhu ,  Nam V. Dang ,  Tirdad Sowlati

发明人： Xiaohua Kong ,  Zhi Zhu ,  Nam V. Dang ,  Tirdad Sowlati

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H04L7/0337

摘要： In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.

摘要翻译： 在特定实施例中，数字电路包括频率检测电路，其可操作以比较与接收信号的连续采样之间的转换有关的信息。 频率检测电路进一步操作以产生控制信号，以响应于具有相同值的预定数量的顺序样本来减小接收信号的采样率。 该数字电路还包括一个数字相位检测器，可操作以提供与频率检测电路的连续样本之间的转换有关的信息。

公开(公告)号：US20140035549A1

公开(公告)日：2014-02-06

申请号：US13564150

申请日：2012-08-01

申请人： Madjid Hafizi ,  Jie Xu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Madjid Hafizi ,  Jie Xu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： G05F3/08

CPC分类号： G05F3/08 ,  H03F2200/03 ,  H04L25/0278 ,  H04L25/028

摘要： A pre-driver circuit generates a driver bias signal based on a swing command, a driver impedance characteristic, and an input signal. A driver receives the driver bias signal and generates, in response, a driver signal having a swing and having an output impedance corresponding to the bias signal. Optionally, the driver receives power from a switchable one of multiple supply rails, according to the swing. Optionally, the driver has voltage controlled resistor elements and the driver bias signal is generated based on the swing command and a replica of the driver voltage controlled resistor elements.

摘要翻译： 预驱动器电路基于摆动指令，驱动器阻抗特性和输入信号产生驱动器偏置信号。 驱动器接收驱动器偏置信号，并作为响应产生具有摆幅并具有对应于偏置信号的输出阻抗的驱动器信号。 可选地，根据摆动，驾驶员从多个供应轨道中的可切换的一个接收功率。 可选地，驱动器具有电压控制的电阻元件，并且基于摆动命令和驱动器电压控制的电阻器元件的副本产生驱动器偏置信号。

公开(公告)号：US08618832B2

公开(公告)日：2013-12-31

申请号：US13197128

申请日：2011-08-03

申请人： Miao Li ,  Nam V. Dang ,  Xiaohua Kong

发明人： Miao Li ,  Nam V. Dang ,  Xiaohua Kong

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/018557 ,  H04L25/0278

摘要： A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor. The impedances of the first and second transistors may be controlled by the first gate control voltage and the second gate control voltage respectively.

摘要翻译： 公开了一种平衡的单端阻抗控制系统。 在特定实施例中，电路包括耦合到第一输出端的第一晶体管和耦合到第二输出端的第二晶体管。 电路还包括第三晶体管和第四晶体管，其中第三晶体管的器件特性基本上与第一晶体管的器件特性匹配，并且第四晶体管的器件特性基本上与第二晶体管的器件特性相匹配。 电路还包括第一控制路径和第二控制路径。 第一路径耦合到第三晶体管，并提供第一轨电压以控制第一晶体管的第一栅控制电压。 第二控制路径耦合到第四晶体管，并提供第二导轨电压以控制第二晶体管的第二栅极控制电压。 第一和第二晶体管的阻抗可以分别由第一栅极控制电压和第二栅极控制电压控制。

公开(公告)号：US08581667B2

公开(公告)日：2013-11-12

申请号：US13294902

申请日：2011-11-11

申请人： Swarna L. Navubothu ,  Cheng Zhong ,  Nam V. Dang ,  Xiaohua Kong

发明人： Swarna L. Navubothu ,  Cheng Zhong ,  Nam V. Dang ,  Xiaohua Kong

IPC分类号： H03K3/03 ,  H03L7/10

CPC分类号： H03L7/0995 ,  H03K3/0315

摘要： A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning voltage. The tuning voltage range extension circuit is configured to selectively change current supplied by the first path as the tuning voltage exceeds a capacity threshold of the first transistor.

摘要翻译： 电路包括包括第一晶体管和第一电流源的第一路径。 第一晶体管响应调谐电压。 电路还包括响应于调谐电压的调谐电压范围扩展电路。 调谐电压范围扩展电路被配置为当调谐电压超过第一晶体管的容量阈值时选择性地改变由第一路径提供的电流。