公开(公告)号：US20060102907A1

公开(公告)日：2006-05-18

申请号：US11228852

申请日：2005-09-16

申请人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

发明人： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

摘要翻译： 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

公开(公告)号：US08865528B2

公开(公告)日：2014-10-21

申请号：US12844356

申请日：2010-07-27

申请人： Jean-Ho Song ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

发明人： Jean-Ho Song ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC分类号： H01L21/84 ,  H01L27/12

CPC分类号： H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

摘要： A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

摘要翻译： 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。

公开(公告)号：US08173492B2

公开(公告)日：2012-05-08

申请号：US12509290

申请日：2009-07-24

申请人： Je-hun Lee ,  Chang-oh Jeong ,  Beom-seok Cho ,  Yang-ho Bae

发明人： Je-hun Lee ,  Chang-oh Jeong ,  Beom-seok Cho ,  Yang-ho Bae

IPC分类号： H01L21/28

CPC分类号： H01L29/4908 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L23/53238 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer.

摘要翻译： 提供一种线结构，形成线的方法，薄膜晶体管（TFT）基板以及制造TFT基板的方法。 导线结构包括设置在下部结构上的阻挡层，设置在阻挡层上的包含铜或铜合金的铜导电层，设置在铜导电层上的包含氮化铜的中间层和设置在中间层上的覆盖层 。

公开(公告)号：US08044398B2

公开(公告)日：2011-10-25

申请号：US12331138

申请日：2008-12-09

申请人： Hong-Long Ning ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Hong-Sick Park ,  Joo-Ae Youn ,  Byeong-Beom Kim ,  Byeong-Jin Lee

发明人： Hong-Long Ning ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Hong-Sick Park ,  Joo-Ae Youn ,  Byeong-Beom Kim ,  Byeong-Jin Lee

IPC分类号： H01L29/04 ,  H01L29/15 ,  H01L27/01 ,  H01L27/12

CPC分类号： G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

摘要： A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.

摘要翻译： 显示基板包括绝缘基板，薄膜晶体管（TFT），像素电极，信号线和焊盘部分。 绝缘基板具有显示区域和围绕显示区域的周边区域。 TFT位于绝缘基板的显示区域。 像素电极在绝缘基板的显示区域中并与TFT电连接。 信号线位于绝缘基板上，并从周边区域向显示区域延伸。 焊盘部分在外围区域中并且电连接到信号线。 衬垫部分形成在绝缘衬底的沟槽中，并且包括延伸到绝缘衬底中的区域。 因此，信号线可以牢固地附接到绝缘基板。

公开(公告)号：US07662715B2

公开(公告)日：2010-02-16

申请号：US11944083

申请日：2007-11-21

申请人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC分类号： H01L21/44

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

摘要翻译： 本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括 铌（Nb），钒（V）和钛（Ti）之一。 因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

公开(公告)号：US20100022055A1

公开(公告)日：2010-01-28

申请号：US12573385

申请日：2009-10-05

申请人： YANG-HO BAE ,  Chang-Oh Jeong ,  Byeong-Beom Kim

发明人： YANG-HO BAE ,  Chang-Oh Jeong ,  Byeong-Beom Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/458 ,  H01L27/124

摘要： A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.

摘要翻译： 在与铟锡氧化物（ITO）或铟锌氧化物（IZO）接触期间显示出期望的接触特性的薄膜晶体管，其中形成包括栅电极的第一导电图案和包括源电极和漏电极的第二导电图案 没有蚀刻处理，包括TFT的TFT基板及其制造方法。 薄膜晶体管包括由第一导电层形成的栅电极，覆盖栅电极的栅极绝缘层，在栅极绝缘层上形成沟道的半导体层; 形成在半导体层上的欧姆接触层，以及由第二导电层和第三导电层形成的源电极和漏电极。 第二导电层包括铝 - 镍合金和氮，并形成在半导体层上。 第三导电层包括铝镍合金，并形成在第二导电层上。

公开(公告)号：US20090236627A1

公开(公告)日：2009-09-24

申请号：US12357207

申请日：2009-01-21

申请人： Jang-Sub Kim ,  Yoon-Ho Kang ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Chang-oh Jeong ,  Soon-Kwon Lim ,  Hong-Sick Park ,  Ning Hong Long ,  Do-Hyun Kim ,  Seung-Jae Jung

发明人： Jang-Sub Kim ,  Yoon-Ho Kang ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Chang-oh Jeong ,  Soon-Kwon Lim ,  Hong-Sick Park ,  Ning Hong Long ,  Do-Hyun Kim ,  Seung-Jae Jung

IPC分类号： H01L33/00 ,  G03F7/26 ,  H01L21/02 ,  C25D7/06 ,  H01L23/52

CPC分类号： C25D5/022 ,  C25D1/04 ,  G02F2001/136295 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1292 ,  H05K3/002 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/246 ,  H05K2201/0108 ,  H05K2201/0347 ,  H05K2203/0568 ,  H05K2203/095 ,  H05K2203/1173

摘要： Provided is a method of forming metal wiring. The method includes forming a photosensitive film pattern on a substrate, hydrophobicizing at least part of the photosensitive film pattern, coating metal ink on the substrate having the photosensitive film pattern, forming a seed layer, and forming a metal layer. Alternatively, a trench is formed by using the photosensitive film pattern as a mask, and metal aerosol is sprayed to form the seed layer and then the metal layer. In this method, there is no need to form a metal thin film on the photosensitive film pattern when the seed layer is formed. As a result, less metal is wasted, which, in turn, significantly reduces manufacturing costs.

摘要翻译： 提供一种形成金属布线的方法。 该方法包括在基板上形成感光膜图案，使至少部分感光膜图案疏水化，在具有感光膜图案的基板上涂覆金属油墨，形成种子层并形成金属层。 或者，通过使用感光膜图案作为掩模形成沟槽，并且喷射金属气溶胶以形成种子层，然后形成金属层。 在该方法中，当形成种子层时，不需要在感光膜图案上形成金属薄膜。 因此，浪费了较少的金属，这又大大降低了制造成本。

公开(公告)号：US20090179203A1

公开(公告)日：2009-07-16

申请号：US12331138

申请日：2008-12-09

申请人： Hong-Long Ning ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Hong-Sick Park ,  Joo-Ae Youn ,  Byeong-Beom Kim ,  Byeong-Jin Lee

发明人： Hong-Long Ning ,  Chang-Oh Jeong ,  Je-Hun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Hong-Sick Park ,  Joo-Ae Youn ,  Byeong-Beom Kim ,  Byeong-Jin Lee

IPC分类号： H01L33/00 ,  H01L21/768 ,  G03F1/00 ,  G03F7/20

CPC分类号： G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908

摘要： A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.

摘要翻译： 显示基板包括绝缘基板，薄膜晶体管（TFT），像素电极，信号线和焊盘部分。 绝缘基板具有显示区域和围绕显示区域的周边区域。 TFT位于绝缘基板的显示区域。 像素电极在绝缘基板的显示区域中并与TFT电连接。 信号线位于绝缘基板上，并从周边区域向显示区域延伸。 焊盘部分在外围区域中并且电连接到信号线。 衬垫部分形成在绝缘衬底的沟槽中，并且包括延伸到绝缘衬底中的区域。 因此，信号线可以牢固地附接到绝缘基板。

公开(公告)号：US20080073674A1

公开(公告)日：2008-03-27

申请号：US11944130

申请日：2007-11-21

申请人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC分类号： H01L29/49

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

摘要翻译： 本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括 铌（Nb），钒（V）和钛（Ti）之一。 因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

公开(公告)号：US07276732B2

公开(公告)日：2007-10-02

申请号：US11234470

申请日：2005-09-23

申请人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

发明人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L29/458 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.

摘要翻译： 薄膜晶体管阵列面板包括由Mo合金层和Cu层构成的源电极和漏电极，Mo合金层的合金元素形成氮化物层作为对Cu层的扩散阻挡层。 可以在Mo合金层和Cu层之间，Mo合金层和半导体层之间或Mo合金层中形成氮化物层。 制造薄膜晶体管阵列面板的方法包括：形成具有第一导电层和第二导电层的数据线，所述第一导电层含有Mo合金，所述第二导电层含有Cu，并进行氮处理，使得 第一导电层中的合金元素形成氮化物层。 在形成第一导电层之前，在形成第一导电层之后，或者在形成第一导电层期间，可以进行氮处理。