公开(公告)号：US6156640A

公开(公告)日：2000-12-05

申请号：US115184

申请日：1998-07-14

Applicant: Meng-Jin Tsai ,  Yimin Huang

Inventor： Meng-Jin Tsai ,  Yimin Huang

IPC: H01L21/027 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/0276 ,  H01L21/76802 ,  H01L21/7684

Abstract: A method for improving the damascene process window for metallization utilizes an anti-reflective coating to increase the precision of the photolithography process. An inter-layer dielectric and an anti-reflective layer are formed in turn on a semiconductor substrate. The inter-layer dielectric is patterned to form the interconnecting line regions. A conductive layer is then deposited on the semiconductor substrate and fills the interconnecting line regions. The chemical mechanical polish is performed to remove a portion of the conductive layer exceeding the interconnect line regions and simultaneously remove residual portion of said anti-reflective layer.

Abstract translation: 用于改进用于金属化的镶嵌工艺窗口的方法利用抗反射涂层来提高光刻工艺的精度。 依次在半导体衬底上形成层间电介质和抗反射层。 将层间电介质图案化以形成互连线区域。 然后将导电层沉积在半导体衬底上并填充互连线区域。 执行化学机械抛光以去除超过互连线区域的导电层的一部分，并同时去除所述抗反射层的残留部分。

公开(公告)号：US6150073A

公开(公告)日：2000-11-21

申请号：US111505

申请日：1998-07-07

Applicant: Yimin Huang

Inventor： Yimin Huang

IPC: H01L21/311 ,  H01L21/768 ,  G03F7/00

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76829

Abstract: A degradation-free, low-permittivity dielectrics patterning process for damascene starts with provision of a substrate, wherein the substrate has a dielectric layer and a via plug formed on it. Then, a inter-metal dielectric layer and an insulating layer are formed in sequence on the dielectric layer. A hard mask layer is next formed on the insulating layer, and is subsequently patterned. An etching process is performed on the insulating layer and the inter metal dielectric layer by using the patterned hard mask layer as a mask to form a metal line trench and expose the via plug. The metal line trench is then filled with metal by forming a metal layer on the hard mask layer. A metal line in the shallow trench is formed by performing chemical mechanical polishing on the metal layer to expose the insulating layer, and then performing post-chemical mechanical polishing cleaning.

Abstract translation: 用于镶嵌的无降解的低介电常数电介质图案化方法从提供衬底开始，其中衬底具有形成在其上的电介质层和通孔塞。 然后，依次在电介质层上形成金属间介电层和绝缘层。 接着在绝缘层上形成硬掩模层，随后将其图案化。 通过使用图案化的硬掩模层作为掩模在绝缘层和金属间介电层上进行蚀刻处理，以形成金属线沟槽并露出通孔塞。 然后通过在硬掩模层上形成金属层来填充金属线沟槽。 通过在金属层上进行化学机械抛光以暴露绝缘层，然后进行后期化学机械抛光清洗，形成浅沟槽中的金属线。

公开(公告)号：US5981395A

公开(公告)日：1999-11-09

申请号：US994157

申请日：1997-12-19

Applicant: Yimin Huang ,  Tri-Rung Yew

Inventor： Yimin Huang ,  Tri-Rung Yew

IPC: H01L21/768 ,  H01L21/302

CPC classification number: H01L21/76829 ,  H01L21/76897

Abstract: A method of fabricating an unlanded metal via of multi-level interconnection. The method is characterized by utilizing damascene scheme to form a metal wiring layer so that the processes are simplified. Moreover, by this method of the invention, a problem of difficulty in filling dielectric material between the metal wiring lines can be avoided and the metal layer does not have to be etched prior to filling the dielectric material. Further more, an etching stop layer is formed over the first inter-metal dielectric layer to avoid overetching during the formation of metal via, which therefore avoid short circuit. Forming the metal wiring lines by damascene scheme allows the etching stop layer to be easily formed over the first dielectric layer, without over etching the metal via.

Abstract translation: 一种制造多层互连的无衬金属通孔的方法。 该方法的特征在于利用镶嵌方案形成金属布线层，从而简化了工艺。 此外，通过本发明的这种方法，可避免难以在金属布线之间填充介电材料的问题，并且在填充电介质材料之前不必对金属层进行蚀刻。 此外，在第一金属间电介质层上形成蚀刻停止层，以避免在形成金属通孔期间的过蚀刻，从而避免短路。 通过镶嵌方案形成金属布线允许蚀刻停止层容易地形成在第一介电层上，而不会过度蚀刻金属通孔。

公开(公告)号：US09412883B2

公开(公告)日：2016-08-09

申请号：US13303083

申请日：2011-11-22

Applicant: Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC: H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L21/822 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20 ,  H01L29/401 ,  H01L29/94

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract translation: 替代栅极工艺中多晶硅MOS电容器的方法和装置。 一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。 公开了通过该方法制造的装置。

公开(公告)号：US08569139B2

公开(公告)日：2013-10-29

申请号：US12913041

申请日：2010-10-27

Applicant: Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

Inventor： Chun-Feng Nieh ,  Ming-Huan Tsai ,  Wei-Han Fan ,  Yimin Huang ,  Chun-Fai Cheng ,  Han-Ting Tsai ,  Chii-Ming Wu

IPC: H01L21/336 ,  H01L21/461

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

公开(公告)号：US20130126955A1

公开(公告)日：2013-05-23

申请号：US13303096

申请日：2011-11-22

Applicant: Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20

Abstract: Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.

Abstract translation: 替代栅极工艺中混合MOS电容器的方法和装置。 公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下 沟渠 并在沟槽中形成高k金属栅极器件。 公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。 公开了另外的混合电容器装置。

公开(公告)号：US20130126953A1

公开(公告)日：2013-05-23

申请号：US13303083

申请日：2011-11-22

Applicant: Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

Inventor： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC: H01L29/94 ,  H01L21/02

CPC classification number: H01L21/822 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20 ,  H01L29/401 ,  H01L29/94

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract translation: 替代栅极工艺中多晶硅MOS电容器的方法和装置。 一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。 公开了通过该方法制造的装置。

公开(公告)号：US20120108026A1

公开(公告)日：2012-05-03

申请号：US12913041

申请日：2010-10-27

Applicant: Chun-Feng NIEH ,  Ming-Huan TSAI ,  Wei-Han FAN ,  Yimin HUANG ,  Chun-Fai CHENG ,  Han-Ting TSAI ,  Chii-Ming WU

Inventor： Chun-Feng NIEH ,  Ming-Huan TSAI ,  Wei-Han FAN ,  Yimin HUANG ,  Chun-Fai CHENG ,  Han-Ting TSAI ,  Chii-Ming WU

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

Abstract translation: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US20110291201A1

公开(公告)日：2011-12-01

申请号：US12787972

申请日：2010-05-26

Applicant: Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

Inventor： Chun-Fai Cheng ,  Fung Ka Hing ,  Ming-Huan Tsai ,  Chun-Feng Nieh ,  Yimin Huang ,  Han-Ting Tsai ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30608 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括硅衬底。 半导体器件包括设置在衬底中的第一和第二区域。 第一和第二区域具有硅化合物材料。 半导体器件包括分别部分地设置在第一和第二区域中的第一和第二源/漏结构。 半导体器件包括设置在衬底上的第一栅极。 第一个门第一个靠近第一个地区。 半导体器件包括设置在衬底上的第二栅极。 第二个门第二个靠近第二个区域。 第二接近度不同于第一接近度。 第一源极/漏极结构和第一栅极是第一晶体管的部分，并且第二源极/漏极结构和第二栅极是第二晶体管的部分。

公开(公告)号：US08058125B1

公开(公告)日：2011-11-15

申请号：US12850390

申请日：2010-08-04

Applicant: Yu-Hsien Lin ,  Inez Fu ,  Yimin Huang

Inventor： Yu-Hsien Lin ,  Inez Fu ,  Yimin Huang

IPC: H01L21/8244

CPC classification number: H01L27/0629

Abstract: The present disclosure provides a poly resistor on a semiconductor device and a method of fabricating the same. In an embodiment, a poly silicon resistor device is formed by providing a substrate having a first region and a second region. A dummy gate stack is formed on the substrate in the first region, wherein the dummy gate stack has a dummy gate stack thickness extending above the substrate. A poly silicon resister is formed on the substrate in the second region, wherein the poly silicon resistor has a poly silicon resistor thickness extending above the substrate a distance which is less than the dummy gate stack thickness. A dopant is implanted into the substrate in the first region thereby forming a source region and a drain region in the first region of the substrate. The dopant is also implanted into the poly silicon resistor. An inter-level dielectric (ILD) layer is formed on the substrate over the dummy gate stack and also over the poly silicon resistor. The ILD layer is planarized, thereby exposing the dummy gate stack and leaving a portion of the ILD layer over the poly silicon resistor. The dummy gate stack is replaced with a high k metal gate while using the portion of the ILD layer over the poly silicon resistor as a mask to protect the poly silicon resistor during replacement of the dummy gate stack with the high k metal gate.

Abstract translation: 本公开在半导体器件上提供多晶硅电阻器及其制造方法。 在一个实施例中，通过提供具有第一区域和第二区域的衬底来形成多晶硅电阻器件。 在第一区域中的基板上形成虚拟栅极堆叠，其中虚拟栅极堆叠具有在基板上方延伸的虚拟栅极叠层厚度。 在第二区域中的基板上形成多晶硅电阻器，其中多晶硅电阻器具有在基板上方延伸的距离小于虚拟栅极叠层厚度的多晶硅电阻器厚度。 掺杂剂注入到第一区域中的衬底中，从而在衬底的第一区域中形成源极区域和漏极区域。 掺杂剂也被注入到多晶硅电阻器中。 在虚拟栅极堆叠上并且还在多晶硅电阻器上方的衬底上形成层间电介质（ILD）层。 ILD层被平坦化，从而暴露虚拟栅极堆叠并将ILD层的一部分留在多晶硅电阻上。 在使用多晶硅电阻器上的ILD层的部分作为掩模的情况下，用高k金属栅极替代伪栅极堆叠，以在用高k金属栅极替换伪栅极堆叠期间保护多晶硅电阻器。