公开(公告)号：US09412883B2

公开(公告)日：2016-08-09

申请号：US13303083

申请日：2011-11-22

申请人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC分类号： H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC分类号： H01L21/822 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20 ,  H01L29/401 ,  H01L29/94

摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

摘要翻译： 替代栅极工艺中多晶硅MOS电容器的方法和装置。 一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。 公开了通过该方法制造的装置。

公开(公告)号：US20130126953A1

公开(公告)日：2013-05-23

申请号：US13303083

申请日：2011-11-22

申请人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang ,  Chung-Hui Chen

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L21/822 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20 ,  H01L29/401 ,  H01L29/94

摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

摘要翻译： 替代栅极工艺中多晶硅MOS电容器的方法和装置。 一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。 公开了通过该方法制造的装置。

公开(公告)号：US09269833B2

公开(公告)日：2016-02-23

申请号：US13303096

申请日：2011-11-22

申请人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

IPC分类号： H01L29/94 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC分类号： H01L29/94 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20

摘要： Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.

摘要翻译： 替代栅极工艺中混合MOS电容器的方法和装置。 公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下 沟渠 并在沟槽中形成高k金属栅极器件。 公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。 公开了另外的混合电容器装置。

公开(公告)号：US20130126955A1

公开(公告)日：2013-05-23

申请号：US13303096

申请日：2011-11-22

申请人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

发明人： Pai-Chieh Wang ,  Tung-Heng Hsieh ,  Yimin Huang

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L29/94 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/20

摘要： Methods and apparatus for hybrid MOS capacitors in replacement gate process. A method is disclosed including patterning a gate dielectric layer and a polysilicon gate layer to form a polysilicon gate region over a substrate; forming an inter-level dielectric layer over the substrate and surrounding the polysilicon gate region; defining polysilicon resistor regions each containing at least one portion of the polysilicon gate region and not containing at least one other portion of the polysilicon gate region, forming dummy gate regions removing the dummy gate regions and the gate dielectric layer underneath the dummy gate regions to leave trenches; and forming high-k metal gate devices in the trenches. A capacitor region including a high-k metal gate and a polysilicon gate next to the high-k metal gate is disclosed. Additional hybrid capacitor apparatuses are disclosed.

摘要翻译： 替代栅极工艺中混合MOS电容器的方法和装置。 公开了一种方法，其包括图案化栅极电介质层和多晶硅栅极层以在衬底上形成多晶硅栅极区域; 在所述衬底上形成层间电介质层并围绕所述多晶硅栅极区域; 限定多晶硅电阻器区域，每个多晶硅电阻器区域包含多晶硅栅极区域的至少一部分并且不包含多晶硅栅极区域的至少一个其他部分，形成伪栅极区域，去除伪栅极区域和伪栅极区域下方的栅极介电层，以留下 沟渠 并在沟槽中形成高k金属栅极器件。 公开了一种包括高k金属栅极和与高k金属栅极相邻的多晶硅栅极的电容器区域。 公开了另外的混合电容器装置。

公开(公告)号：US10163724B2

公开(公告)日：2018-12-25

申请号：US13409999

申请日：2012-03-01

申请人： Pai-Chieh Wang ,  Yimin Huang

发明人： Pai-Chieh Wang ,  Yimin Huang

IPC分类号： H01L21/8238

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.

公开(公告)号：US09595477B2

公开(公告)日：2017-03-14

申请号：US13010028

申请日：2011-01-20

申请人： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

发明人： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

IPC分类号： H01L21/4763 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

摘要翻译： 描述了一种方法，其包括提供衬底并形成邻接衬底上的栅极结构的第一间隔物材料层。 第二间隔材料层邻近并邻接栅极结构并且覆盖第一间隔物层形成。 然后分别同时蚀刻第一间隔材料层和第二间隔材料层以形成第一和第二间隔物。 在衬底上形成（例如，生长）外延区域，其包括与第一和第二间隔物中的每一个的界面。 随后可以移除第二间隔物，并且保留在器件上的第一间隔物减小ILD间隙填充的纵横比。 第一间隔物的实例组成是SiCN。

公开(公告)号：US20120187459A1

公开(公告)日：2012-07-26

申请号：US13010028

申请日：2011-01-20

申请人： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

发明人： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

IPC分类号： H01L29/772 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

摘要翻译： 描述了一种方法，其包括提供衬底并形成邻接衬底上的栅极结构的第一间隔物材料层。 第二间隔材料层邻近并邻接栅极结构并且覆盖第一间隔物层形成。 然后分别同时蚀刻第一间隔材料层和第二间隔材料层以形成第一和第二间隔物。 在衬底上形成（例如，生长）外延区域，其包括与第一和第二间隔物中的每一个的界面。 随后可以移除第二间隔物，并且保留在器件上的第一间隔物减小ILD间隙填充的纵横比。 第一间隔物的实例组成是SiCN。

公开(公告)号：US07378740B2

公开(公告)日：2008-05-27

申请号：US11196038

申请日：2005-08-02

申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

公开(公告)号：US06680248B2

公开(公告)日：2004-01-20

申请号：US09991131

申请日：2001-11-20

申请人： Yimin Huang ,  Tri-Rung Yew

发明人： Yimin Huang ,  Tri-Rung Yew

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/76807

摘要： A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

摘要翻译： 形成双镶嵌结构的方法包括以下步骤：提供其上形成有第一导电层的衬底，然后在衬底上顺序形成第一电介质层，抗反射层和第二电介质层。 接下来，对第一电介质层，抗反射层和第二电介质层进行图案化以形成暴露导电层的第一开口。 此后，第二介电层被图案化以在第一导电层上方的位置形成沟槽（或第二开口）。 沟槽和第一开口一起形成双镶嵌结构的开口。 最后，将第二导电材料沉积到开口和沟槽中以形成导电线和双镶嵌结构。

公开(公告)号：US06388326B2

公开(公告)日：2002-05-14

申请号：US09800574

申请日：2001-03-08

申请人： Hermen Liu ,  Yimin Huang

发明人： Hermen Liu ,  Yimin Huang

IPC分类号： H01L2328

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/48463 ,  H01L2924/0001 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.

摘要翻译： 本发明提供了半导体芯片上的接合焊盘，从而避免了在封装过程中的互连期间剥离焊盘。 焊盘用于将半导体芯片中的集成电路与外部电路电连接。 半导体芯片包括位于半导体芯片的表面上的预定区域中的第一电介质层，位于半导体芯片的表面上的第二电介质层，其中第一电介质层比第二介电层硬， 以及位于第一电介质层上的用于将半导体芯片中的集成电路（IC）电连接到外部电路的接合焊盘。