公开(公告)号：US08885394B2

公开(公告)日：2014-11-11

申请号：US13604743

申请日：2012-09-06

Applicant: Byung-Ho Kang ,  Yong Jin Yoon ,  Young Jae Son

Inventor： Byung-Ho Kang ,  Yong Jin Yoon ,  Young Jae Son

IPC: G11C11/00 ,  G11C7/12 ,  G11C7/18 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C7/18

Abstract: A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.

Abstract translation: 存储器件包括布置在全局位线和互补全局位线之间的部分，并且具有设置在第一和第二存储器单元组之间并连接在全局位线和互补全局位线之间的部分控制单元，以提供第一读取 信号和第二读信号。 信号转换器接收第一和第二读取信号，并产生指示存储在存储单元中的数据值的稳定受控读取信号。 锁存单元接收并锁存由信号转换器提供的受控读信号以产生锁存的读信号。

公开(公告)号：US07400177B2

公开(公告)日：2008-07-15

申请号：US11627794

申请日：2007-01-26

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: G11C7/00

CPC classification number: H03K3/356139

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

Abstract translation: 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

公开(公告)号：US07295489B2

公开(公告)日：2007-11-13

申请号：US11037602

申请日：2005-01-18

Applicant: Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

Inventor： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

IPC: G11C7/00

CPC classification number: G11C7/1087 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093

Abstract: A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

Abstract translation: 一种用于在双倍数据速率（DDR）存储器件中采样和写入数据的方法和电路，能够确保足够的设置和保持余量而不考虑操作频率。 使用第一路径控制信号将第一和第二采样输入数据传送到第一路径。 使用第二路径控制信号将第三和第四采样输入数据传送到第二路径。 第一和第二路径控制信号是相位相差一个半周期。 与第一外部时钟信号的上升沿或下降沿同步地连续采样第一至第四数据; 响应于第一路径控制信号（与外部时钟信号的下降沿同步产生），采样的第一数据被链接到第一路径上，并且采样的第二数据被链接到第二路径上。 响应于写入时钟信号将第一路径上的第一数据和第二路径上的第二数据写入存储器单元。

公开(公告)号：US06933758B2

公开(公告)日：2005-08-23

申请号：US10308453

申请日：2002-12-03

Applicant: Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

Inventor： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

IPC: G06F1/12 ,  G06F1/10 ,  H03K5/15 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087

CPC classification number: H03L7/0814 ,  H03L7/087

Abstract: A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

Abstract translation: 同步镜延迟电路包括用于延迟来自时钟缓冲电路的参考时钟信号的延迟监视电路。 正向延迟阵列顺序地延迟延迟监视电路的输出时钟信号以产生延迟时钟信号，并且镜像控制电路在延迟时钟信号中检测与参考时钟信号同步的延迟时钟信号。 后向延迟阵列延迟由镜像控制电路延迟的时钟信号，并且时钟驱动器接收反向延迟阵列的输出时钟信号以产生内部时钟信号。 当前向延迟阵列的延迟时钟信号与参考信号同步时，锁定范围控制电路控制传送到延迟监视器电路的每个时钟信号的延迟时间达到传送到时钟驱动器的每个信号的延迟时间量 时钟信号。

公开(公告)号：US20120319753A1

公开(公告)日：2012-12-20

申请号：US13527214

申请日：2012-06-19

Applicant: Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

Inventor： Min-Su Kim ,  Yong-Jin Yoon ,  Ji-Kyum Kim

IPC: H03L7/00

CPC classification number: H03K5/05

Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.

Abstract translation: 集成电路装置包括：时钟延迟电路，被配置为接收时钟信号和脉冲信号并从其产生输出信号。 时钟延迟电路被配置为响应于时钟信号的第一状态而将输出信号转换到第一状态，并且响应于脉冲信号的第一状态转换而将输出信号转变到第二状态。 集成电路装置还包括脉冲发生器电路，其被配置为接收时钟信号和输出信号并从其产生脉冲信号。 脉冲发生器电路被配置为响应于时钟信号向第二状态的转变而产生脉冲信号中的第一状态转换，并且响应于输出信号向第二状态的转变而产生脉冲信号中的第二状态转换 州。

公开(公告)号：US20110154142A1

公开(公告)日：2011-06-23

申请号：US12944787

申请日：2010-11-12

Applicant: Young-Jae SON ,  Yong-Jin YOON ,  Uk-Rae CHO

Inventor： Young-Jae SON ,  Yong-Jin YOON ,  Uk-Rae CHO

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/31725 ,  G06F11/24

Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.

Abstract translation: 用于片上系统的测试装置包括顺序逻辑电路和测试电路。 顺序逻辑电路通过根据串行时钟信号和串行使能信号将串行输入信号转换为并行格式产生测试输入信号，并通过将测试输出信号转换成串行格式来响应于 串行时钟信号和串行使能信号。 测试电路包括至少一个延迟单元，其与执行片上系统的原始功能的逻辑电路分离，响应于系统时钟信号，使用测试输入信号对至少一个延迟单元执行延迟测试 和测试使能信号，并将测试输出信号提供给顺序逻辑电路，其中测试输出信号表示延迟测试的结果。

公开(公告)号：US20070139084A1

公开(公告)日：2007-06-21

申请号：US11627794

申请日：2007-01-26

Applicant: Nam-Seog KIM ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog KIM ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: H03K5/22

CPC classification number: H03K3/356139

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

Abstract translation: 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

公开(公告)号：US20050146365A1

公开(公告)日：2005-07-07

申请号：US11031129

申请日：2005-01-07

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: G11C11/40 ,  G11C7/00 ,  G11C8/00 ,  G11C11/407 ,  H03K5/13 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081

CPC classification number: H03L7/0812 ,  H03K5/133 ,  H03K5/135

Abstract: An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

Abstract translation: 提供一种用于产生用于获取精确同步的内部时钟信号的装置。 该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列 镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列 以及产生内部时钟信号的输出缓冲器。 可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。

公开(公告)号：US20130083592A1

公开(公告)日：2013-04-04

申请号：US13604743

申请日：2012-09-06

Applicant: BYUNG-HO KANG ,  YONG JIN YOON ,  YOUNG JAE SON

Inventor： BYUNG-HO KANG ,  YONG JIN YOON ,  YOUNG JAE SON

IPC: G11C7/00

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C7/18

Abstract: A memory device includes sections arranged between a global bit line and a complementary global bit line, and having a section control unit disposed between first and second memory cell groups and connected between the global bit line and the complementary global bit line to provide a first read signal and a second read signal. A signal converter receives the first and second read signals and generates a stable controlled read signal indicative of a data value stored in the memory cell. A latch unit receives and latches the controlled read signal provided by the signal converter to generate a latched read signal.

Abstract translation: 存储器件包括布置在全局位线和互补全局位线之间的部分，并且具有设置在第一和第二存储器单元组之间并连接在全局位线和互补全局位线之间的部分控制单元，以提供第一读取 信号和第二读信号。 信号转换器接收第一和第二读取信号，并产生指示存储在存储单元中的数据值的稳定受控读取信号。 锁存单元接收并锁存由信号转换器提供的受控读信号以产生锁存的读信号。

公开(公告)号：US20080055964A1

公开(公告)日：2008-03-06

申请号：US11850130

申请日：2007-09-05

Applicant: Sang-beom KANG ,  Yong-jin YOON ,  Qi WANG

Inventor： Sang-beom KANG ,  Yong-jin YOON ,  Qi WANG

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/009

Abstract: A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.

Abstract translation: 非易失性存储器件包括第一电压产生单元，第二电压产生单元，第一电路块和放电单元。 第一电压产生单元产生具有第一量值的第一电压。 第二电压产生单元产生具有大于第一幅值的第二幅度的第二电压。 第一电路块通过输入节点选择性地接收第一电压或第二电压。 放电单元在输入节点已经被充电的时间点与第二电压之间和输入节点接收到第一电压的时间点之间对输入节点进行放电。