公开(公告)号：US08681475B2

公开(公告)日：2014-03-25

申请号：US13590270

申请日：2012-08-21

申请人： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

发明人： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

IPC分类号： H01G4/06

CPC分类号： H01G4/12 ,  H01G4/228 ,  H01G4/30

摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.

摘要翻译： 这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构，其中层叠有电介质片的多层陶瓷电容器和形成在其两端的外部端子电极，其上形成有内部电极的电介质片，以及 外部端子电极与内部电极并联连接，其中内部电极被设置为与电路板平行，外部端子电极通过导电材料接合到电路板的焊盘，并且接合高度 Ts）低于多层陶瓷电容器的电路板和底面之间的间隙（Ta）和多层陶瓷电容器的下表面的覆盖层的厚度（Tc）之和， 层状陶瓷电容器，从而可以大大降低振动噪声。

公开(公告)号：US08385048B2

公开(公告)日：2013-02-26

申请号：US13529766

申请日：2012-06-21

申请人： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Young Hoon Song ,  Mi Hee Lee

发明人： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Young Hoon Song ,  Mi Hee Lee

IPC分类号： H01G4/06

CPC分类号： H01G4/01 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

摘要： There is provided a chip type laminated capacitor, including: a ceramic body including a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 □m or less; first and second outer electrodes formed on both ends of the ceramic body in a length direction; first and second band parts formed to extend inwardly of the ceramic body in the length direction on a length-width (L-W) plane from the first and second outer electrodes and having different lengths; and third and fourth band parts formed to extend inwardly of the ceramic body in the length direction on a length-thickness (L-T) plane from the first and second outer electrodes and having different lengths.

摘要翻译： 提供了一种片式叠层电容器，其包括：陶瓷体，其包括厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层; 第一外电极和第二外电极，其在长度方向上形成在陶瓷体的两端; 第一和第二带部分形成为在第一和第二外部电极的长度（L-W）平面上沿长度方向在陶瓷体的内部延伸并具有不同的长度; 以及第三和第四带部分，其形成为在长度方向上在距第一和第二外部电极的长度 - 厚度（L-T）平面上延伸到陶瓷体的内侧并具有不同的长度。

公开(公告)号：US20120298407A1

公开(公告)日：2012-11-29

申请号：US13481348

申请日：2012-05-25

申请人： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

发明人： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

IPC分类号： H05K1/16

CPC分类号： H05K1/111 ,  H01G4/12 ,  H01G4/30 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/2045 ,  Y02P70/611 ,  Y02P70/613

摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon. The mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, in which a dielectric layer on which inner electrodes are disposed is stacked and external electrode terminals connecting the inner electrodes in parallel are disposed on both ends thereof, wherein the inner electrodes of the multi-layered ceramic capacitor and the circuit board are disposed so as to be a horizontal direction to connect the external electrode terminals with a land on the circuit board by a conductive material and a ratio of a bonding area ASOLEDER of the conductive material to the area AMLCC of the external electrode terminals AMLCC is set to be less than 1.4, thereby remarkably reducing the vibration noise.

摘要翻译： 这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构。 其上设置有多层陶瓷电容器的电路板的安装结构，其中布置有内部电极的电介质层，并且将其内部电极并联连接的外部电极端子设置在其两端，其中内部电极 将多层陶瓷电容器和电路板设置成水平方向，以通过导电材料将导电材料的外部电极端子与电路板上的焊盘接合，并且将导电材料的接合面积ASOLEDER与 外部电极端子AMLCC的面积AMLCC被设定为小于1.4，从而显着地降低了振动噪声。

公开(公告)号：US20120152604A1

公开(公告)日：2012-06-21

申请号：US13331619

申请日：2011-12-20

申请人： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

发明人： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

IPC分类号： H05K1/18 ,  H05K3/00 ,  H01G4/30

CPC分类号： H01G2/065 ,  H01G4/232 ,  H01G4/30 ,  H05K3/3442 ,  H05K13/022 ,  H05K2201/10015 ,  H05K2203/166 ,  Y02P70/613 ,  Y10T29/49124

摘要： The present invention provides a method of mounting a circuit board having thereon a multi-layered ceramic capacitor and a land pattern of a circuit board for the same. The method of mounting a circuit board having thereon a multi-layered ceramic capacitor on which a plurality of dielectric sheet having internal electrodes formed thereon are stacked and the external terminal electrodes connected to the internal electrodes in parallel are formed on both ends thereof includes conductively connecting lands of a circuit board to the external terminal electrodes in such a way that internal electrode layers of the multi-layered ceramic capacitor and the circuit board are arranged in a horizontal direction, wherein a height TS of conductive material to conductively connect the external terminal electrodes to the lands is less than ⅓ of a thickness TMLCC of the multi-layered ceramic capacitor.

摘要翻译： 本发明提供了一种安装电路板的方法，其上具有多层陶瓷电容器和用于其的电路板的焊盘图案。 在其上堆叠有多层陶瓷电容器的电路板的方法，其上形成有形成有内部电极的多个电介质层，并且在其两端形成有与内部电极并联连接的外部端子电极的方法包括导电连接 电路板的接地部分以外部端子电极的方式使多层陶瓷电容器和电路板的内部电极层沿水平方向排列，其中导电材料的高度TS导电连接外部端子电极 到土地的厚度小于多层陶瓷电容器的厚度TMLCC的1/3。

公开(公告)号：US20110309895A1

公开(公告)日：2011-12-22

申请号：US13022129

申请日：2011-02-07

申请人： Young Ghyu AHN ,  Sang Soo Park ,  Dong Seok Park ,  Sung Jin Park ,  Yong Sun Park ,  Bong Sup Lim

发明人： Young Ghyu AHN ,  Sang Soo Park ,  Dong Seok Park ,  Sung Jin Park ,  Yong Sun Park ,  Bong Sup Lim

IPC分类号： H03H7/01

CPC分类号： H03H7/01 ,  H01P1/20345

摘要： A multilayer filter includes: a ceramic body in which a plurality of dielectric layers are laminated; an external ground electrode provided on an outer surface of the ceramic body and connected to a ground; an inductor pattern electrode provided on at least one of the dielectric layers and having one end connected to the external ground electrode; a capacitor pattern electrode provided on at least one of the dielectric layers; an external terminal electrode electrically connecting the inductor pattern electrode to the capacitor pattern electrode and forming a closed loop for generating inductance through the external ground electrode; and a variable dielectric layer provided between the capacitor pattern electrode and the inductor pattern electrode and adjusting a magnitude of inductance generated by the inductor pattern electrode.

摘要翻译： 多层过滤器包括：层叠有多个电介质层的陶瓷体; 外部接地电极，设置在陶瓷体的外表面上，并连接到地面; 电感器图案电极，设置在所述电介质层中的至少一个上，并且一端连接到所述外部接地电极; 设置在至少一个所述电介质层上的电容器图案电极; 外部端子电极，电连接电感器图形电极到电容器图案电极，并形成用于通过外部接地电极产生电感的闭环; 以及设置在电容器图案电极和电感器图案电极之间的可变介电层，并且调节由电感器图案电极产生的电感的大小。

公开(公告)号：US09099242B2

公开(公告)日：2015-08-04

申请号：US13588696

申请日：2012-08-17

申请人： Young Ghyu Ahn ,  Sang Soo Park ,  Min Cheol Park ,  Se Hwa Jeong

发明人： Young Ghyu Ahn ,  Sang Soo Park ,  Min Cheol Park ,  Se Hwa Jeong

IPC分类号： H05K1/16 ,  H01G4/005 ,  H05K1/02 ,  H01G4/30

CPC分类号： H01G4/005 ,  H01G4/30 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09427 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/2045 ,  Y02P70/611

摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.

摘要翻译： 层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

公开(公告)号：US08638543B2

公开(公告)日：2014-01-28

申请号：US13588876

申请日：2012-08-17

申请人： Young Ghyu Ahn ,  Min Cheol Park ,  Doo Young Kim ,  Sang Soo Park

发明人： Young Ghyu Ahn ,  Min Cheol Park ,  Doo Young Kim ,  Sang Soo Park

IPC分类号： H01G4/06 ,  H01G4/005

CPC分类号： H01G4/30 ,  B65B9/04 ,  B65B15/04 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H05K1/181 ,  H05K2201/10015

摘要： A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.

摘要翻译： 层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的第一外部电极和第二外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 上下层形成在有源层的厚度方向的上部和下部上，下覆盖层的厚度大于上覆盖层的厚度; 以及与下覆盖层内的电容的形成无关地设置的附加电极层。

公开(公告)号：US20130050894A1

公开(公告)日：2013-02-28

申请号：US13590270

申请日：2012-08-21

申请人： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

发明人： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

IPC分类号： H01G4/228 ,  H01G4/12

CPC分类号： H01G4/12 ,  H01G4/228 ,  H01G4/30

摘要： Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.

摘要翻译： 这里公开了一种其上具有多层陶瓷电容器的电路板的安装结构，其中层叠有电介质片的多层陶瓷电容器和形成在其两端的外部端子电极，其上形成有内部电极的电介质片，以及 外部端子电极与内部电极并联连接，其中内部电极被设置为与电路板平行，外部端子电极通过导电材料接合到电路板的焊盘，并且接合高度 Ts）低于多层陶瓷电容器的电路板和底面之间的间隙（Ta）和多层陶瓷电容器的下表面的覆盖层的厚度（Tc）之和， 层状陶瓷电容器，从而可以大大降低振动噪声。

公开(公告)号：US08351181B1

公开(公告)日：2013-01-08

申请号：US13531242

申请日：2012-06-22

申请人： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Young Hoon Song ,  Mi Hee Lee

发明人： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Min Cheol Park ,  Young Hoon Song ,  Mi Hee Lee

IPC分类号： H01G4/06

CPC分类号： H01G4/1272 ,  H01G2/065 ,  H01G4/005 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30

摘要： There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 μm or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 μm or less.

摘要翻译： 提供一种芯片型层叠电容器，其包括：陶瓷体，其通过层叠厚度等于其中包含的晶粒的平均粒径的10倍以上且为3μm以下的电介质层而形成; 第一和第二外部电极; 第一内部电极，其一端与形成有第二外部电极的陶瓷体的一个端面一起形成第一边缘，而另一端通向第一外部电极; 以及第二内部电极，其一端与形成有第一外部电极的陶瓷体的另一个端面一起形成第二边缘，另一端通向第二外部电极，其中第一和第二边缘具有不同的宽度 在200μm以下的条件下。

公开(公告)号：US20120327556A1

公开(公告)日：2012-12-27

申请号：US13531237

申请日：2012-06-22

申请人： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

发明人： Young Ghyu AHN ,  Byoung Hwa Lee ,  Min Cheol Park ,  Sang Soo Park ,  Dong Seok Park

IPC分类号： H01G4/12

CPC分类号： H01G4/12 ,  H01G4/012 ,  H01G4/30

摘要： There is provided a multilayer ceramic capacitor, including: a multilayer body in which a plurality of dielectric layers are stacked in a thickness direction; and inner electrode layers formed within the multilayer body and including first and second inner electrodes disposed to be opposed to each other; wherein a ratio (MA1/CA1) of MA1 to CA1 is between 0.07 and 0.20, wherein CA1 represents an area of the multilayer body in a cross section of the multilayer body taken in a length and thickness direction, and MA1 represents an area of a first margin part in the cross section of the multilayer body taken in the length and thickness direction, the first margin part being a portion of the multilayer body, other than a first capacitance forming part thereof in which the first and second inner electrodes overlap in the thickness direction.

摘要翻译： 提供了一种多层陶瓷电容器，包括：多层体，其中多个电介质层在厚度方向上堆叠; 以及形成在所述多层体内并且包括彼此相对设置的第一和第二内部电极的内部电极层; 其中MA1与CA1的比率（MA1 / CA1）在0.07和0.20之间，其中CA1表示在长度和厚度方向上取下的多层体的横截面中的多层体的面积，MA1表示 第一边缘部分是沿着长度和厚度方向截取的第一边缘部分，第一边缘部分是多层体的一部分，除了第一电容形成部分之外，第一和第二内部电极在其中重叠 厚度方向。