Abstract:
A mask that is capable of forming a thin-film transistor (TFT) with improved electrical characteristics is presented. The mask includes a drain mask pattern, a source mask pattern and a light-adjusting pattern. The drain mask pattern blocks light for forming a drain electrode. The source mask pattern blocks light for forming a source electrode and faces the drain mask pattern. A distance between the drain and source mask patterns is no more than the resolution of an exposing device. The light-adjusting pattern is formed between end portions of the source mask pattern and the drain mask pattern to block at least some light from entering a space between the source and drain mask patterns.
Abstract:
A bridge for heterogeneous QoS networks is provided. The bridge comprises an UPnP QoS processing unit, a bridge function unit and at least two of network drive drivers. The UPnP QoS processing unit collects connection information connected through the networks and QoS requirement information thereof through an UPnP QoS structure. The bridge function unit establishes and releases connection by allocating resources based on the collected connection information and QoS requirement information, and performs a bridging operation according to connection information of a received frame. At least two of network device drivers are physically connected to the networks.
Abstract:
Embodiments of the present invention relate to a liquid crystal display and a driving method thereof. According to an embodiment, the liquid crystal display comprises a pixel electrode having a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode electrically separated from each other. The liquid crystal display comprises a first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a third thin film transistor connected to the third subpixel electrode, and a fourth thin film transistor connected to the second subpixel electrode and the third subpixel electrode. The liquid crystal display comprises a first gate line connected to the first to third thin film transistors, a second gate line connected to the fourth thin film transistor, a data line connected to the first and second thin film transistors, and a storage electrode line connected to the third thin film transistor.
Abstract:
A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.
Abstract:
The present invention relates to a liquid crystal display and a method of manufacturing the same. A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate, a first conductor arranged on the first substrate, a first insulating layer arranged on the first substrate and the first conductor, a second insulating layer arranged on the first insulating layer, a semiconductor layer arranged on the second insulating layer, and a second conductor arranged on the semiconductor layer and the second insulating layer. The semiconductor layer is made of an oxide semiconductor, and the second conductor includes a source electrode, a drain electrode, and a storage electrode line.
Abstract:
A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.
Abstract:
Provided are an apparatus and a method for injecting liquid crystal into a hollow optic fiber. The apparatus includes: a first holder and a second holder each of which has a fluid passage for holding corresponding one end of the hollow optic fiber to be communicated with the fluid passage a container connected to a tube disposed with a valve at the fluid passage of the second holder and storing liquid crystal; an air supplying device connected to the first holder and the container through tubes having a plurality of valves to select an air passage for making the hollow optic fiber vacuous by sucking air out of the hollow optic fiber and forcedly injecting liquid crystal into the hollow optic fiber by supplying an air pressure.
Abstract:
Provided are an apparatus and a method for injecting liquid crystal into a hollow optic fiber. The apparatus includes: a first holder and a second holder each of which has a fluid passage for holding corresponding one end of the hollow optic fiber to be communicated with the fluid passage a container connected to a tube disposed with a valve at the fluid passage of the second holder and storing liquid crystal; an air supplying device connected to the first holder and the container through tubes having a plurality of valves to select an air passage for making the hollow optic fiber vacuous by sucking air out of the hollow optic fiber and forcedly injecting liquid crystal into the hollow optic fiber by supplying an air pressure.
Abstract:
A display apparatus includes a substrate including a display area having a transmissive region and a reflective region and a peripheral area surrounding the display area, a gate line and a data line formed on the substrate and crossing each other to define a pixel area in the display area, a gate electrode and a common electrode, wherein the gate electrode branches from the gate line in the pixel area and the common electrode is spaced apart from the gate electrode, a source electrode and a drain electrode formed on the gate electrode, wherein the source electrode branches from the data line and the drain electrode is spaced apart from the source electrode, and a reflective electrode formed in the pixel area by extending the drain electrode into the pixel area and provided with at least one opening to define the transmissive region and the reflective region.
Abstract:
A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.