公开(公告)号：US12130692B2

公开(公告)日：2024-10-29

申请号：US17993562

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Donny Yi ,  Oleksandr Khodorkovsky ,  Leonardo De Paula Rosa Piga ,  Wonje Choi ,  Dana G. Lewis ,  Sriram Sambamurthy

IPC: G06F1/32 ,  G06F1/3287

CPC classification number: G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US20240004453A1

公开(公告)日：2024-01-04

申请号：US17854858

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashwini Chandrashekhara Holla ,  Alexander S. Duenas ,  Xinzhe Li ,  Indrani Paul ,  Karthik Rao

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more operating frequencies of the cores based on the profiling.

公开(公告)号：US20240004444A1

公开(公告)日：2024-01-04

申请号：US17855054

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Dana Glenn Lewis ,  Brett Danier Anil Ramautarsingh ,  Jeffrey Ka-Chun Lui ,  Prasanthy Loganaathan ,  Jun Huang ,  Ho Hin Lau ,  Zhidong Xu

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.

公开(公告)号：US11556250B2

公开(公告)日：2023-01-17

申请号：US16939814

申请日：2020-07-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. Kotra ,  Karthik Rao ,  Joseph L. Greathouse

IPC: G06F3/06

Abstract: A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.

公开(公告)号：US11886224B2

公开(公告)日：2024-01-30

申请号：US16945519

申请日：2020-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Leonardo De Paula Rosa Piga ,  Karthik Rao ,  Indrani Paul ,  Mahesh Subramony ,  Kenneth Mitchell ,  Dana Glenn Lewis ,  Sriram Sambamurthy ,  Wonje Choi

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/30

CPC classification number: G06F9/5027 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/5055 ,  G06F9/5094 ,  G06F9/30098 ,  G06F2209/5021

Abstract: A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.

公开(公告)号：US11829222B2

公开(公告)日：2023-11-28

申请号：US17127681

申请日：2020-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

IPC: G06F1/28 ,  G01R31/40 ,  G06F1/30

CPC classification number: G06F1/28 ,  G01R31/40 ,  G06F1/30

Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

公开(公告)号：US11543877B2

公开(公告)日：2023-01-03

申请号：US17219097

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Donny Yi ,  Oleksandr Khodorkovsky ,  Leonardo De Paula Rosa Piga ,  Wonje Choi ,  Dana G. Lewis ,  Sriram Sambamurthy

IPC: G06F1/32 ,  G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US20190296644A1

公开(公告)日：2019-09-26

申请号：US16440838

申请日：2019-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Miguel Rodriguez ,  Karthik Rao

IPC: H02M3/158 ,  G05F1/56 ,  G05F1/46 ,  G05F1/575

Abstract: An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.