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公开(公告)号：US11054883B2
公开(公告)日：2021-07-06
申请号：US16011476
申请日：2018-06-18
IPC分类号： G06F1/324
摘要： A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.
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公开(公告)号：US11543877B2
公开(公告)日：2023-01-03
申请号：US17219097
申请日：2021-03-31
发明人： Karthik Rao , Indrani Paul , Donny Yi , Oleksandr Khodorkovsky , Leonardo De Paula Rosa Piga , Wonje Choi , Dana G. Lewis , Sriram Sambamurthy
IPC分类号： G06F1/32 , G06F1/3287
摘要： An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.
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公开(公告)号：US12130692B2
公开(公告)日：2024-10-29
申请号：US17993562
申请日：2022-11-23
发明人： Karthik Rao , Indrani Paul , Donny Yi , Oleksandr Khodorkovsky , Leonardo De Paula Rosa Piga , Wonje Choi , Dana G. Lewis , Sriram Sambamurthy
IPC分类号： G06F1/32 , G06F1/3287
CPC分类号： G06F1/3287
摘要： An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.
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公开(公告)号：US20180364782A1
公开(公告)日：2018-12-20
申请号：US16011476
申请日：2018-06-18
IPC分类号： G06F1/32
摘要： A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.
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5.发明授权公开(公告)号：US10928789B2
公开(公告)日：2021-02-23
申请号：US15950172
申请日：2018-04-11
IPC分类号： G05B15/02
摘要： A processing unit includes a plurality of subsystem control modules. Each subsystem control module includes a set of one or more inputs that receives a set of one or more external signals and a set of one or more monitored outputs from a hardware subsystem corresponding to the subsystem control module, and a set of configuration outputs for controlling one or more configuration settings of the hardware subsystem. The subsystem control module determines the one or more configuration settings based on the set of monitored outputs and on one or more targets derived from the set of external signals.
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公开(公告)号：US11886224B2
公开(公告)日：2024-01-30
申请号：US16945519
申请日：2020-07-31
发明人： Leonardo De Paula Rosa Piga , Karthik Rao , Indrani Paul , Mahesh Subramony , Kenneth Mitchell , Dana Glenn Lewis , Sriram Sambamurthy , Wonje Choi
CPC分类号： G06F9/5027 , G06F9/48 , G06F9/4806 , G06F9/4843 , G06F9/4881 , G06F9/4893 , G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5033 , G06F9/5044 , G06F9/5055 , G06F9/5094 , G06F9/30098 , G06F2209/5021
摘要： A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.
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7.发明申请公开(公告)号：US20190317461A1
公开(公告)日：2019-10-17
申请号：US15950172
申请日：2018-04-11
IPC分类号： G05B15/02
摘要： A processing unit includes a plurality of subsystem control modules. Each subsystem control module includes a set of one or more inputs that receives a set of one or more external signals and a set of one or more monitored outputs from a hardware subsystem corresponding to the subsystem control module, and a set of configuration outputs for controlling one or more configuration settings of the hardware subsystem. The subsystem control module determines the one or more configuration settings based on the set of monitored outputs and on one or more targets derived from the set of external signals.
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公开(公告)号：US12056535B2
公开(公告)日：2024-08-06
申请号：US17137925
申请日：2020-12-30
申请人： ATI Technologies ULC
发明人： Indrani Paul , Leonardo De Paula Rosa Piga , Mahesh Subramony , Sonu Arora , Donald Cherepacha , Adam N C Clark
IPC分类号： G06F9/50 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3296 , G06F11/30 , G06F11/34
CPC分类号： G06F9/505 , G06F1/3203 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/5016 , G06F11/3037 , G06F11/3062 , G06F11/3409 , G06F2209/501 , G06F2209/508
摘要： Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on an integrated circuit (IC), and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.
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公开(公告)号：US20220206850A1
公开(公告)日：2022-06-30
申请号：US17137925
申请日：2020-12-30
申请人： ATI Technologies ULC
发明人： Indrani Paul , Leonardo De Paula Rosa Piga , Mahesh Subramony , Sonu Arora , Donald Cherepacha , Adam N. C. Clark
IPC分类号： G06F9/50 , G06F11/30 , G06F1/3203
摘要： Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.
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