公开(公告)号：US11543877B2

公开(公告)日：2023-01-03

申请号：US17219097

申请日：2021-03-31

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Donny Yi ,  Oleksandr Khodorkovsky ,  Leonardo De Paula Rosa Piga ,  Wonje Choi ,  Dana G. Lewis ,  Sriram Sambamurthy

IPC: G06F1/32 ,  G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US12130692B2

公开(公告)日：2024-10-29

申请号：US17993562

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Donny Yi ,  Oleksandr Khodorkovsky ,  Leonardo De Paula Rosa Piga ,  Wonje Choi ,  Dana G. Lewis ,  Sriram Sambamurthy

IPC: G06F1/32 ,  G06F1/3287

CPC classification number: G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US20240004453A1

公开(公告)日：2024-01-04

申请号：US17854858

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashwini Chandrashekhara Holla ,  Alexander S. Duenas ,  Xinzhe Li ,  Indrani Paul ,  Karthik Rao

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more operating frequencies of the cores based on the profiling.

公开(公告)号：US20240004444A1

公开(公告)日：2024-01-04

申请号：US17855054

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Dana Glenn Lewis ,  Brett Danier Anil Ramautarsingh ,  Jeffrey Ka-Chun Lui ,  Prasanthy Loganaathan ,  Jun Huang ,  Ho Hin Lau ,  Zhidong Xu

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.

公开(公告)号：US20240192760A1

公开(公告)日：2024-06-13

申请号：US18080582

申请日：2022-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Donny Yi ,  Karthik Rao

IPC: G06F1/3296

CPC classification number: G06F1/3296

Abstract: A disclosed technique includes in response to a trigger to power a functional element of a device to a lower power state, operating a set of backup state elements for the functional element in a lower power mode; and resuming operation of the functional element and the backup state elements in a higher power state.

公开(公告)号：US10725670B2

公开(公告)日：2020-07-28

申请号：US16052055

申请日：2018-08-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. Kotra ,  Karthik Rao ,  Joseph L. Greathouse

IPC: G06F3/06

Abstract: A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.

公开(公告)号：US11194634B2

公开(公告)日：2021-12-07

申请号：US16220827

申请日：2018-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Karthik Rao ,  Shomit N. Das ,  Xudong An ,  Wei Huang

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  H04L29/08 ,  G06F1/3206 ,  G06F13/40 ,  G06F3/06 ,  H04N19/436

Abstract: In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.

公开(公告)号：US11137809B2

公开(公告)日：2021-10-05

申请号：US16228036

申请日：2018-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Karthik Rao ,  Wei Huang ,  Xudong An ,  Manish Arora ,  Joseph L. Greathouse

IPC: G06F1/26 ,  G06F1/20

Abstract: A plurality of thermal electric cooler (TEC) elements are formed in a TEC grid structure. Control logic dynamically varies a supply current supplied to each TEC element (or group of TEC elements) in the TEC grid based on changes in power density respectively associated with areas cooled by each of the TEC elements or group of TEC elements.

公开(公告)号：US20210064444A1

公开(公告)日：2021-03-04

申请号：US16552065

申请日：2019-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Karthik Rao ,  Abhinav Vishnu

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/54 ,  G06N3/08

Abstract: Systems, apparatuses, and methods for proactively managing inter-processor network links are disclosed. A computing system includes at least a control unit and a plurality of processing units. Each processing unit of the plurality of processing units includes a compute module and a configurable link interface. The control unit dynamically adjusts a clock frequency and a link width of the configurable link interface of each processing unit based on a data transfer size and layer computation time of a plurality of layers of a neural network so as to reduce execution time of each layer. By adjusting the clock frequency and the link width of the link interface on a per-layer basis, the overlapping of communication and computation phases is closely matched, allowing layers to complete more quickly.

公开(公告)号：US20240085964A1

公开(公告)日：2024-03-14

申请号：US18515131

申请日：2023-11-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

IPC: G06F1/28 ,  G01R31/40 ,  G06F1/30

CPC classification number: G06F1/28 ,  G01R31/40 ,  G06F1/30

Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.