公开(公告)号：US20180018105A1

公开(公告)日：2018-01-18

申请号：US15252889

申请日：2016-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/28 ,  G11C7/10

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0674 ,  G06F13/287 ,  G06F13/4022 ,  G11C7/1072

Abstract: In one form, a memory controller has a memory channel controller including a command queue and an arbiter. The command queue stores memory access requests including a sub-channel number in a virtual controller mode. The arbiter is coupled to the command queue to select memory access commands from the command queue according to predetermined criteria. In the virtual controller mode, the arbiter selects from among the memory access requests in each sub-channel independently using the predetermined criteria, and sends selected memory access requests to a corresponding one of a plurality of sub-channels. In another form, a data processing system includes a plurality of memory channels and such a memory controller coupled to the plurality of sub-channels.

公开(公告)号：US12154657B2

公开(公告)日：2024-11-26

申请号：US17853418

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro

IPC: G06F12/00 ,  G11C7/10 ,  G11C7/22

Abstract: An arbiter is operable to pick commands from a command queue for dispatch to a memory. The arbiter includes a traffic throttle circuit for mitigating excess power usage increases in coordination with one or more additional arbiters. The traffic throttle circuit includes a monitoring circuit and a throttle circuit. The monitoring circuit is for measuring a number of read and write commands picked by the arbiter and the one or more additional arbiters over a first predetermined period of time. The throttle circuit, responsive to a low activity state, limits a number of read and write commands issued by the arbiter during a second predetermined period of time.

公开(公告)号：US12118247B2

公开(公告)日：2024-10-15

申请号：US18086942

申请日：2022-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

Abstract: A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.

公开(公告)号：US20230197123A1

公开(公告)日：2023-06-22

申请号：US17556958

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Pouya Najafi Ashtiani ,  Craig Daniel Eaton ,  Kedarnath Balakrishnan

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14

CPC classification number: G11C7/1069 ,  G11C7/1096 ,  G11C7/222 ,  G11C5/14

Abstract: A method and apparatus for performing a simulated write in a computer system includes, responsive to a scheduled memory operation determined by a memory controller, sending a simulated write operation to a physical layer circuitry (PHY) to increase circuit power without enabling the output of the PHY until the memory operation begins. Responsive to the memory operation being complete, sending a simulated write operation to the PHY to decrease circuit power.

公开(公告)号：US11675659B2

公开(公告)日：2023-06-13

申请号：US15375076

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： James R. Magro ,  Ruihua Peng ,  Anthony Asaro ,  Kedarnath Balakrishnan ,  Scott P. Murphy ,  YuBin Yao

IPC: G06F11/10 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F11/1016 ,  G06F11/10 ,  G06F13/1626 ,  G06F13/4022

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

公开(公告)号：US11561862B2

公开(公告)日：2023-01-24

申请号：US16887904

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F11/00 ,  G06F11/14 ,  G11C11/406

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue, and transmits the commands from the memory interface queue to a memory channel connected to at least one dynamic random access memory (DRAM). The transmitted commands are stored in a replay queue. A number of activate commands to a memory region of the DRAM is counted. Based on this count, a refresh control circuit signals that an urgent refresh command should be sent to the memory region. In response to detecting a designated type of error, a recovery sequence initiates to re-transmit memory commands from the replay queue. Designated error conditions can cause the recovery sequence to restart. If an urgent refresh command is pending when such a restart occurs, the recovery sequence is interrupted to allow the urgent refresh command to be sent.

公开(公告)号：US11531601B2

公开(公告)日：2022-12-20

申请号：US16729994

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F11/14 ,  G06F3/06

Abstract: A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.

公开(公告)号：US11474942B2

公开(公告)日：2022-10-18

申请号：US16959496

申请日：2018-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G11C7/00 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G11C16/34 ,  G06F15/78 ,  G11C16/04 ,  G11C16/10 ,  G06F12/0897 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time.

公开(公告)号：US20210374006A1

公开(公告)日：2021-12-02

申请号：US16887904

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F11/14 ,  G11C11/406

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue, and transmits the commands from the memory interface queue to a memory channel connected to at least one dynamic random access memory (DRAM). The transmitted commands are stored in a replay queue. A number of activate commands to a memory region of the DRAM is counted. Based on this count, a refresh control circuit signals that an urgent refresh command should be sent to the memory region. In response to detecting a designated type of error, a recovery sequence initiates to re-transmit memory commands from the replay queue. Designated error conditions can cause the recovery sequence to restart. If an urgent refresh command is pending when such a restart occurs, the recovery sequence is interrupted to allow the urgent refresh command to be sent.

公开(公告)号：US11099786B2

公开(公告)日：2021-08-24

申请号：US16730070

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: A memory controller interfaces with a non-volatile storage class memory (SCM) module over a heterogeneous memory channel, and includes a command queue for receiving memory access commands. A memory interface queue is coupled to the command queue for holding outgoing commands. A non-volatile command queue is coupled to the command queue for storing non-volatile read commands that are placed in the memory interface queue. An arbiter selects entries from the command queue, and places them in the memory interface queue for transmission over a heterogeneous memory channel. A control circuit is coupled to the heterogeneous memory channel for receiving a ready response from the non-volatile SCM module indicating that responsive data is available for a non-volatile read command, and in response to receiving the ready response, causing a send command to be placed in the memory interface queue for commanding the non-volatile SCM module to send the responsive data.