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    PROCESSOR SUPPORT FOR SOFTWARE-LEVEL CONTAINMENT OF ROW HAMMER ATTACKS
    11.
    发明公开
    PROCESSOR SUPPORT FOR SOFTWARE-LEVEL CONTAINMENT OF ROW HAMMER ATTACKS 审中-公开

    公开(公告)号：US20230195889A1

    公开(公告)日：2023-06-22

    申请号：US17559520

    申请日：2021-12-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F21/55 ,  G11C11/406 ,  G06F21/79

    CPC classification number: G06F21/554 ,  G11C11/40618 ,  G11C11/40611 ,  G06F21/79

    Abstract: A method and apparatus for mitigating row hammer attacks is provided. A row hammer alert is generated by a component of a memory architecture controlling operation of a memory device. The component may be a memory controller, coherency logic, or data fabric. The component obtains a physical address of an aggressor row that caused the alert and obtains an identifier of an execution context corresponding to the physical address. The component generates an error message for a processing device, the error message including the identifier of the execution context. The processing device retrieves the error message when performing a context switch. The processing device then generates an event received by the operating system. The operating system then takes action to reduce row hammer by the execution context, such as ending, restarting, or throttling the execution context.

    METHOD AND APPARATUS FOR PROVIDING DISTRIBUTED CHECKPOINTING
    13.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING DISTRIBUTED CHECKPOINTING 审中-公开

    公开(公告)号：US20180018242A1

    公开(公告)日：2018-01-18

    申请号：US15207943

    申请日：2016-07-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sergey Blagodurov ,  Taniya Siddiqua ,  Vilas Sridharan

    IPC: G06F11/14 ,  G06F3/06

    CPC classification number: G06F11/1471 ,  G06F2201/805 ,  G06F2201/84

    Abstract: Methods and apparatus presented herein provide distributed checkpointing in a multi-node system, such as a network of servers in a data center. When checkpointing of application state data is needed in a node, the methods and apparatus determine whether checkpoint memory space is available in the node for checkpointing the application state data. If not enough checkpoint memory space is available in the node, the methods and apparatus request and find additional checkpoint memory space from other nodes in the system. In this manner, the methods and apparatus can checkpoint the application state data into available checkpoint memory spaces distributed among a plurality of nodes. This allows for high bandwidth and low latency checkpointing operations in the multi-node system.

    Software only intra-compute unit redundant multithreading for GPUs
    15.
    发明授权
    Software only intra-compute unit redundant multithreading for GPUs 有权
    用于GPU的软件内部计算单元冗余多线程

    公开(公告)号：US09367372B2

    公开(公告)日：2016-06-14

    申请号：US13920574

    申请日：2013-06-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander Lyashevsky ,  Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F9/38 ,  G06F9/52 ,  G06F11/00 ,  G06F11/16

    CPC classification number: G06F11/00 ,  G06F9/3851 ,  G06F9/52 ,  G06F11/1608 ,  G06F11/1633 ,  G06F11/1637 ,  G06F11/1654 ,  G06F11/1687 ,  G06F11/202 ,  G06F11/2038 ,  G06F11/2041 ,  G06F11/2048 ,  G06F2201/825 ,  G06F2201/83

    Abstract: A system, method and computer program product to execute a first and a second work-item, and compare the signature variable of the first work-item to the signature variable of the second work-item. The first and the second work-items are mapped to an identifier via software. This mapping ensures that the first and second work-items execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-items independently, the underlying computation of the first and second work-item can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-items are compared only at specified comparison points.

    Abstract translation: 一种用于执行第一和第二工作项目的系统，方法和计算机程序产品，并且将第一工作项目的签名变量与第二工作项目的签名变量进行比较。 第一个和第二个工作项通过软件映射到一个标识符。 此映射确保第一个和第二个工作项完全相同的数据完全相同的代码，而不会更改底层硬件。 通过独立地执行第一和第二工作项目，可以验证第一和第二工件的基础计算。 此外，系统性能基本上不受影响，因为第一和第二工作项目的执行结果仅在指定的比较点进行比较。

    Determining the vulnerability of multi-threaded program code to soft errors
    16.
    发明授权
    Determining the vulnerability of multi-threaded program code to soft errors 有权
    确定多线程程序代码对软错误的脆弱性

    公开(公告)号：US09292418B2

    公开(公告)日：2016-03-22

    申请号：US14266131

    申请日：2014-04-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vilas Sridharan ,  Mark E. Wilkening ,  Sudhanva Gurumurthi

    IPC: G06F9/44 ,  G06F11/36 ,  G06F11/34 ,  G06F9/48

    CPC classification number: G06F11/3672 ,  G06F9/4843 ,  G06F11/34 ,  G06F11/3419 ,  G06F11/3471 ,  G06F11/3612

    Abstract: The described embodiments include a program code testing system that determines the vulnerability of multi-threaded program code to soft errors. For multi-threaded program code, two to more threads from the program code may access shared architectural structures while the program code is being executed. The program code testing system determines accesses of architectural structures made by the two or more threads of the multi-threaded program code and uses the determined accesses to determine a time for which the program code is exposed to soft errors. From this time, the program code testing system determines a vulnerability of the program code to soft errors.

    Abstract translation: 所描述的实施例包括程序代码测试系统，其确定多线程程序代码对软错误的脆弱性。 对于多线程程序代码，程序代码中的两个到更多的线程可以在执行程序代码时访问共享架构结构。 程序代码测试系统确定由多线程程序代码的两个或多个线程进行的架构结构的访问，并使用所确定的访问来确定程序代码暴露于软错误的时间。 从这时起，程序代码测试系统将程序代码的漏洞确定为软错误。

    Using Redundant Transactions to Verify the Correctness of Program Code Execution
    17.
    发明申请
    Using Redundant Transactions to Verify the Correctness of Program Code Execution 有权
    使用冗余事务来验证程序代码执行的正确性

    公开(公告)号：US20150067278A1

    公开(公告)日：2015-03-05

    申请号：US14013252

    申请日：2013-08-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F3/06

    CPC classification number: G06F12/0811

    Abstract: In the described embodiments, a processor core (e.g., a GPU core) receives a section of program code to be executed in a transaction from another entity in a computing device. The processor core sends the section of program code to one or more compute units in the processor core to be executed in a first transaction and concurrently executed in a second transaction, thereby creating a “redundant transaction pair.” When the first transaction and the second transaction are completed, the processor core compares a read-set of the first transaction to a read-set of the second transaction and compares a write-set of the first transaction to a write-set of the second transaction. When the read-sets and the write-sets match and no transactional error condition has occurred, the processor core allows results from the first transaction to be committed to an architectural state of the computing device.

    Abstract translation: 在所描述的实施例中，处理器核心（例如，GPU核心）从计算设备中的另一个实体接收要在事务中执行的程序代码部分。 处理器核心将程序代码段发送到处理器核心中的一个或多个计算单元，以在第一事务中执行并在第二事务中同时执行，从而创建“冗余事务对”。当第一事务和第二事务 处理器核心将第一事务的读取集合与第二事务的读取集进行比较，并将第一事务的写入集合与第二事务的写入集进行比较。 当读取集合和写入集合匹配并且没有发生事务错误条件时，处理器核心允许来自第一事务的结果被提交到计算设备的架构状态。

    Host-level error detection and fault correction
    18.
    发明授权
    Host-level error detection and fault correction 有权

    公开(公告)号：US12013752B2

    公开(公告)日：2024-06-18

    申请号：US17841864

    申请日：2022-06-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan

    IPC: G06F11/10 ,  G06F11/07

    CPC classification number: G06F11/1004 ,  G06F11/0772 ,  G06F11/102 ,  G06F11/1068

    Abstract: A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.

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