公开(公告)号：US08918655B2

公开(公告)日：2014-12-23

申请号：US14082940

申请日：2013-11-18

Applicant: Apple Inc.

Inventor： Kenneth L. Herman ,  Matthew J. Byom ,  Michael J. Smith ,  Tahoma M. Toelkes

IPC: G06F12/14 ,  G06F21/72 ,  G06F21/79 ,  G11C16/10 ,  G11C16/22 ,  G06F12/02

CPC classification number: G06F12/1408 ,  G06F12/0246 ,  G06F21/72 ,  G06F21/79 ,  G06F2221/2107 ,  G11C16/10 ,  G11C16/22

Abstract: Systems, apparatuses, and methods are provided for whitening and managing data for storage in non-volatile memories, such as Flash memory. In some embodiments, an electronic device such as media player is provided, which may include a system-on-a-chip (SoC) and a non-volatile memory. The SoC may include SoC control circuitry and a memory interface that acts as an interface between the SoC control circuitry and the non-volatile memory. The SoC can also include an encryption module, such as a block cipher based on the Advanced Encryption Standard (AES). The memory interface can direct the encryption module to whiten all types of data prior to storage in the non-volatile memory, including sensitive data, non-sensitive data, and memory management data. This can, for example, prevent or reduce program-disturb problems or other read/write/erase reliability issues.

Abstract translation: 提供了用于白化和管理数据以存储在诸如闪存的非易失性存储器中的系统，装置和方法。 在一些实施例中，提供诸如媒体播放器的电子设备，其可以包括片上系统（SoC）和非易失性存储器。 SoC可以包括SoC控制电路和用作SoC控制电路和非易失性存储器之间的接口的存储器接口。 SoC还可以包括加密模块，例如基于高级加密标准（AES）的块密码。 存储器接口可以指示加密模块在存储在非易失性存储器之前对所有类型的数据进行白化，包括敏感数据，非敏感数据和存储器管理数据。 这可以例如防止或减少程序干扰问题或其他读/写/擦除可靠性问题。

公开(公告)号：US20140215182A1

公开(公告)日：2014-07-31

申请号：US13750013

申请日：2013-01-25

Applicant: APPLE INC.

Inventor： Josh P. de Cesare ,  Gerard R. Williams, III ,  Michael J. Smith ,  Wei-Han Lien

IPC: G06F9/30

CPC classification number: G06F9/322 ,  G06F9/30076

Abstract: In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.

Abstract translation: 在一个实施例中，集成电路包括至少一个处理器。 处理器可以包括被配置为存储处理器的复位向量地址的复位向量基地址寄存器。 响应于复位，处理器可以被配置为捕获输入上的复位向量地址，更新复位向量基地址寄存器。 当复位释放时，处理器可以在复位向量地址处启动指令执行。 集成电路还可以包括耦合以提供复位向量地址的逻辑电路。 逻辑电路可以包括可用复位向量地址编程的寄存器。 更具体地，在一个实施例中，寄存器可以通过由处理器发出的写入操作来编程（例如，存储器映射的写入操作）。 因此，复位矢量地址可以在集成电路中可编程，并且可以不时地改变。

公开(公告)号：US11714924B2

公开(公告)日：2023-08-01

申请号：US17469591

申请日：2021-09-08

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

CPC classification number: G06F21/72 ,  G06F12/0246 ,  G06F12/1027 ,  G06F12/1408 ,  G06F21/78 ,  H04L9/0861 ,  H04L9/0894 ,  G06F2212/7206 ,  G06F2212/7208 ,  G06F2221/2143 ,  H04L2209/12

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US20210117265A1

公开(公告)日：2021-04-22

申请号：US17114388

申请日：2020-12-07

Applicant: Apple Inc.

Inventor： Christopher J. Noe ,  Joshua H. Berlin ,  Joseph J. Castro ,  Hardik K. Doshi ,  Joel N. Kerr ,  Kerry J. Kopp ,  Michael J. Smith

IPC: G06F11/07 ,  G06F11/30

Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.

公开(公告)号：US20200257829A1

公开(公告)日：2020-08-13

申请号：US16859634

申请日：2020-04-27

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  H04L9/08 ,  G06F21/78 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/02

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US20190179695A1

公开(公告)日：2019-06-13

申请号：US16147330

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Christopher J. Noe ,  Joshua H. Berlin ,  Joseph J. Castro ,  Hardik K. Doshi ,  Joel N. Kerr ,  Kerry J. Kopp ,  Michael J. Smith

IPC: G06F11/07

Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.

公开(公告)号：US09959120B2

公开(公告)日：2018-05-01

申请号：US13750013

申请日：2013-01-25

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Gerard R. Williams, III ,  Michael J. Smith ,  Wei-Han Lien

IPC: G06F1/32 ,  G06F9/32 ,  G06F9/30

CPC classification number: G06F9/322 ,  G06F9/30076

Abstract: In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.

公开(公告)号：US09256551B2

公开(公告)日：2016-02-09

申请号：US13963457

申请日：2013-08-09

Applicant: Apple Inc.

Inventor： Timothy R. Paaske ,  David S. Warren ,  Michael J. Smith ,  Diarmuid P. Ross ,  Weihua Mao

IPC: H04L29/06 ,  G06F12/14 ,  H04L9/12 ,  G06F21/60 ,  G06F21/72 ,  G06F21/85 ,  G06F21/87 ,  G09C1/00

CPC classification number: G06F12/1408 ,  G06F21/602 ,  G06F21/72 ,  G06F21/85 ,  G06F21/87 ,  G09C1/00 ,  H04L9/12 ,  H04L2209/12

Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.

Abstract translation: 在一个实施例中，外围接口控制器可以包括内联密码引擎，其可以对通过外围接口发送的数据进行加密，并解密从外围接口接收的数据。 加密可能对连接到正在接收/提供数据的外设接口的设备是透明的。 在一个实施例中，外围接口控制器包括在芯片上的系统（SOC）中，该系统还包括被配置为耦合到存储器的存储器控​​制器。 存储器可以以片上芯片或封装的封装形式安装在SOC上。 未加密的数据可以存储在存储器中以供SOC的其他部分使用（例如处理器，片上外设等）。 用于加密/解密数据的密钥可能保留在SOC内。

公开(公告)号：US11307921B2

公开(公告)日：2022-04-19

申请号：US17114388

申请日：2020-12-07

Applicant: Apple Inc.

Inventor： Christopher J. Noe ,  Joshua H. Berlin ,  Joseph J. Castro ,  Hardik K. Doshi ,  Joel N. Kerr ,  Kerry J. Kopp ,  Michael J. Smith

IPC: G06F11/07 ,  G06F11/30

Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.

公开(公告)号：US11138346B2

公开(公告)日：2021-10-05

申请号：US16859634

申请日：2020-04-27

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.