公开(公告)号：US20250036575A1

公开(公告)日：2025-01-30

申请号：US18914382

申请日：2024-10-14

Applicant: Arm Limited

Inventor： Jason PARKER ,  Andrew Brookfield SWAINE ,  Yuval ELAD ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/109

Abstract: Processing circuitry 10 performs processing in one of at least three domains 82, 84, 86, 88. Address translation circuitry 16 translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces 61 selected based at least on the current domain. The domains include a root domain 82 for managing switching between other domains. The physical address spaces 61 include a root physical address space associated with the root domain 82, separate from physical address spaces associated with other domains.

公开(公告)号：US20230205709A1

公开(公告)日：2023-06-29

申请号：US17996269

申请日：2021-04-14

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Yuval ELAD ,  Alexander Donald Charles CHADWICK ,  Andrew Brookfield SWAINE ,  Carlos GARCIA-TOBIN

IPC: G06F12/14

CPC classification number: G06F12/1483 ,  G06F12/1441 ,  G06F12/145

Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.

公开(公告)号：US20210073403A1

公开(公告)日：2021-03-11

申请号：US16564282

申请日：2019-09-09

Applicant: Arm Limited

Inventor： Andrew Brookfield SWAINE

IPC: G06F21/62 ,  G06F3/06

Abstract: A memory system component comprises transaction handling circuitry to receive memory access transactions. Each memory access transaction specifies at least: an issuing domain identifier which indicates an issuing security domain specified by an issuing master device for the memory access transaction, where the issuing security domain is one of a plurality of security domains; a target address; and a security check indication which indicates whether it is already known that the memory access transaction would pass a security checking procedure. The security checking procedure determines whether the memory access transaction indicating said issuing security domain is authorised to access the target address, based on control data indicative of which of the plurality of security domains are allowed to access the target address. The memory system component comprises control circuitry to determine, on the basis of the security check indication, whether the security checking procedure still needs to be performed.

公开(公告)号：US20190018777A1

公开(公告)日：2019-01-17

申请号：US15646406

申请日：2017-07-11

Applicant: ARM Limited

Inventor： Andrew Brookfield SWAINE

IPC: G06F12/0846 ,  G06F12/1045 ,  G06F12/0808 ,  G06F12/128 ,  G06F12/1009

Abstract: An apparatus has an address translation cache with entries for storing address translation data. Partition configuration storage circuitry stores multiple sets of programmable configuration data each corresponding to a partition identifier identifying a corresponding software execution environment or master device and specifying a corresponding subset of entries of the cache. In response to a translation lookup request specifying a target address and a requesting partition identifier, control circuitry triggers a lookup operation to identify whether the target address hits or misses in the corresponding subset of entries specified by the set of partition configuration data for the requesting partition identifier.

公开(公告)号：US20180004678A1

公开(公告)日：2018-01-04

申请号：US15614644

申请日：2017-06-06

Applicant: ARM LIMITED

Inventor： Michal Karol BOGUSZ ,  Quinn CARTER ,  Andrew Brookfield SWAINE

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/0215 ,  G06F12/1009 ,  G06F2212/65 ,  G06F2212/654 ,  G06F2212/68

Abstract: An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.

公开(公告)号：US20240241845A1

公开(公告)日：2024-07-18

申请号：US18098360

申请日：2023-01-18

Applicant: Arm Limited

Inventor： Guanghui GENG ,  Andrew Brookfield SWAINE

IPC: G06F13/16 ,  G06F12/1027 ,  G06F12/14 ,  G06F13/22

CPC classification number: G06F13/1689 ,  G06F12/1027 ,  G06F12/1491 ,  G06F13/225

Abstract: Circuitry comprises a memory to store data defining a set of one or more command queues each associated with a respective memory address space, each command queue defining successive commands for execution from a queue head to a queue tail, the commands being selected from a set of commands comprising synchronization commands and one or more other commands defining memory management operations for a given memory address space, in which completion of a synchronization command is dependent upon one or more completion criteria indicating that all commands from any of the command queues which are earlier than the synchronization command in an execution order have completed; and command processing circuitry to execute the commands; in which the command processing circuitry is configured to maintain a linked list of entries having a list order, each entry defining a respective one of the command queues, in which the command processing circuitry is configured to execute commands at the head of command queues, the command queues being defined by prevailing entries of the linked list of entries in the list order; and in which, for a current occupancy of the linked list at a given stage, the given stage being a given stage of executing commands from command queues defined by entries of the linked list, the command processing circuitry is configured to execute a synchronization command first in the list order and to detect, within that current occupancy of the linked list at the given stage, any further synchronization commands at the head of command queues which are defined by entries of the linked list later in the list order, the command processing circuitry applying, for any such further synchronization commands, the completion criteria of the synchronization command at the head of a given command queue, the given command queue being defined by an entry of the linked list earliest in the list order so as to treat any such further synchronization commands as having been completed.

公开(公告)号：US20230418765A1

公开(公告)日：2023-12-28

申请号：US17850072

申请日：2022-06-27

Applicant: Arm Limited

Inventor： Andrew David TUNE ,  Andrew Brookfield SWAINE

IPC: G06F12/121 ,  G06F12/0891 ,  G06F12/06

CPC classification number: G06F12/121 ,  G06F12/0891 ,  G06F12/0646

Abstract: An apparatus comprises a cache comprising a plurality of cache entries, and cache replacement control circuitry to select, in response to a cache request specifying a target address missing in the cache, a victim cache entry to be replaced with a new cache entry. The cache request specifies a partition identifier indicative of an execution environment associated with the cache request. The victim cache entry is selected based on re-reference interval prediction (RRIP) values for a candidate set of cache entries. The RRIP value for a given cache entry is indicative of a relative priority with which the given cache entry is to be selected as the victim cache entry. Configurable replacement policy configuration data is selected based on the partition identifier, and the RRIP value of the new cache entry is set to an initial value selected based on the selected configurable replacement policy configuration data.
[FIG. 1]

公开(公告)号：US20210303478A1

公开(公告)日：2021-09-30

申请号：US17197425

申请日：2021-03-10

Applicant: Arm Limited

Inventor： Andrew Brookfield SWAINE

IPC: G06F12/1027

Abstract: Memory management apparatus comprises input circuitry to receive a translation request defining a first memory address within a first memory address space; prediction circuitry to generate a predicted second memory address within a second memory address space as a predicted translation of the first memory address, the predicted second memory address being a predetermined function of the first memory address; control circuitry to initiate processing of the predicted second memory address; translation and permission circuitry to perform an operation to generate a translated second memory address for the first memory address associated with permission information to indicate whether memory access is permitted to the translated second memory address; and output circuitry to provide the translated second memory address as a response to the translation request when the permission information indicates that access is permitted to the translated second memory address.

公开(公告)号：US20210026568A1

公开(公告)日：2021-01-28

申请号：US16898781

申请日：2020-06-11

Applicant: Arm Limited

Inventor： Andrew Brookfield SWAINE ,  Peter Andrew RIOCREUX

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/1009

Abstract: An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.

公开(公告)号：US20180157590A1

公开(公告)日：2018-06-07

申请号：US15825633

申请日：2017-11-29

Applicant: ARM Limited

Inventor： Håkan Lars-Göran PERSSON ,  Ian Rudolf BRATT ,  Andrew Brookfield SWAINE ,  Bruce James MATHEWSON

IPC: G06F12/0831 ,  G06F13/16

CPC classification number: G06F12/0833 ,  G06F13/1668 ,  G06F2212/621

Abstract: A filter unit comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter unit has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.