公开(公告)号：US09620200B1

公开(公告)日：2017-04-11

申请号：US15081869

申请日：2016-03-26

Applicant: ARM Limited

Inventor： Sanjay Mangal ,  Gus Yeung ,  Martin Jay Kinkade ,  Rahul Mathur ,  Bal S. Sandhu ,  George McNeil Lattimore

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  H01L27/11 ,  H01L27/1104

Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

公开(公告)号：US10571516B2

公开(公告)日：2020-02-25

申请号：US15691722

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore

IPC: G01R31/3187 ,  G01R31/28 ,  H03K5/24 ,  H01L21/8238 ,  H03M1/66 ,  G06F11/25

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include converter circuitry that operates to provide a drive current. The integrated circuit may include process detector circuitry having multiple drive strength devices that are driven by the drive current from the converter circuitry. The multiple drive strength devices may provide multiple drive strength signals based on the drive current. The integrated circuit may include comparator circuitry having a comparator that receives the multiple drive strength signals from the multiple drive strength devices, detects a voltage difference between the multiple drive strength signals, and provides an output signal based on the detected voltage difference.

公开(公告)号：US20190325959A1

公开(公告)日：2019-10-24

申请号：US15960365

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Brian Tracy Cline ,  George McNeil Lattimore ,  Bal S. Sandhu

IPC: G11C14/00 ,  G11C13/00 ,  G11C7/06

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.

公开(公告)号：US20190325919A1

公开(公告)日：2019-10-24

申请号：US15960405

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Shidhartha Das ,  George McNeil Lattimore ,  Brian Tracy Cline

IPC: G11C5/06 ,  G11C14/00 ,  G11C8/10

Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

公开(公告)号：US20190236315A1

公开(公告)日：2019-08-01

申请号：US16378256

申请日：2019-04-08

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

IPC: G06F21/75 ,  G06F1/28

CPC classification number: G06F21/755 ,  G06F1/28

Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

公开(公告)号：US10255462B2

公开(公告)日：2019-04-09

申请号：US15185789

申请日：2016-06-17

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

IPC: H04L29/06 ,  G06F21/75 ,  H04L9/00 ,  G09C1/00

Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

公开(公告)号：US11822705B2

公开(公告)日：2023-11-21

申请号：US17536696

申请日：2021-11-29

Applicant: Arm Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

IPC: H04L29/06 ,  G06F21/75 ,  G06F1/28

CPC classification number: G06F21/755 ,  G06F1/28

Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

公开(公告)号：US11423985B2

公开(公告)日：2022-08-23

申请号：US16582743

申请日：2019-09-25

Applicant: Arm Limited

Inventor： Fernando Garcia Redondo ,  Shidhartha Das ,  Glen Arnold Rosendale ,  George McNeil Lattimore ,  Mudit Bhargava

IPC: G11C13/00

Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.

公开(公告)号：US20220083696A1

公开(公告)日：2022-03-17

申请号：US17536696

申请日：2021-11-29

Applicant: Arm Limited

Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

IPC: G06F21/75 ,  G06F1/28

Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

公开(公告)号：US10964379B2

公开(公告)日：2021-03-30

申请号：US16183655

申请日：2018-11-07

Applicant: Arm Limited

Inventor： Rainer Herberholz ,  George McNeil Lattimore ,  Amit Chhabra

IPC: H03K3/03 ,  G11C11/412 ,  G11C11/417 ,  H03K5/00

Abstract: Various implementations described herein refer to an integrated circuit having a row of bitcells that are chained together in series to operate as a ring oscillator. Each bitcell in the row of bitcells has multiple transistors that are independent of additional transistors to form the ring oscillator. The multiple transistors of each bitcell in the row of bitcells are arranged to function as an inverter.