中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.041 seconds)

    ADAPTING THE USAGE CONFIGURATION OF INTEGRATED CIRCUIT INPUT-OUTPUT PADS
    11.
    发明申请
    ADAPTING THE USAGE CONFIGURATION OF INTEGRATED CIRCUIT INPUT-OUTPUT PADS 审中-公开

    公开(公告)号：US20180164375A1

    公开(公告)日：2018-06-14

    申请号：US15533479

    申请日：2015-12-22

    Applicant: ARM LIMITED

    Inventor： James Edward MYERS ,  Parameshwarappa Anand Kumar SAVANTH

    IPC: G01R31/317

    CPC classification number: G01R31/31715 ,  G01R31/31721 ,  G01R31/31724 ,  G06F11/27

    Abstract: Techniques for implementing a self-test procedure of an integrated circuit are provided, where the self-test procedure comprises testing for an electrical connection between first and second input-output pads of the integrated circuit. A control device is capable of adapting a functional configuration of usage of the first and second input-output pads in dependence on presence of the electrical connection. A corresponding integrated circuit, printed circuit and method are also provided. These techniques allow the integrated circuit to be used in a variety of contexts, without requiring physical customisation of the integrated circuit to adapt it to its usage context, in particular where connections from the context to the pads of the integrated circuit may be made to individual pads in some contexts or may span more than one pad in other contexts.

    POWER SIGNAL INTERFACE
    13.
    发明申请
    POWER SIGNAL INTERFACE 有权
    电源信号接口

    公开(公告)号：US20160170465A1

    公开(公告)日：2016-06-16

    申请号：US14907945

    申请日：2014-06-16

    Applicant: ARM LIMITED

    Inventor： David Walter FLYNN ,  James Edward MYERS

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/3024 ,  G06F11/3058 ,  G06F11/3096 ,  G06F13/00 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Mechanisms are provided for energy management signalling with an apparatus for processing data, such as a system-on-chip integrated circuit (2). Processing circuitry (6, 8, 10) is coupled to consumer energy interface circuitry (14, 16, 18) which communicates with energy management circuitry (4). The energy management signals which are communicated include a static power consumption signal indicative of a level of power consumption which is independent of processing operations being performed and a dynamic power consumption signal indicative of a level of dynamic power consumption which is dependent upon the processing operations being performed.

    Abstract translation: 提供了用于处理数据的装置的能量管理信令的机制，例如片上系统集成电路（2）。 处理电路（6,8,10）耦合到与能量管理电路（4）通信的消费者能量接口电路（14,16,18）。 所传送的能量管理信号包括指示与所执行的处理操作无关的功率消耗水平的静态功耗信号，以及指示取决于处理操作的动态功耗水平的动态功耗信号 执行。

    INTEGRITY MONITORING FOR FLEXIBLE MATERIAL
    15.
    发明公开
    INTEGRITY MONITORING FOR FLEXIBLE MATERIAL 审中-公开

    公开(公告)号：US20230172287A1

    公开(公告)日：2023-06-08

    申请号：US17543070

    申请日：2021-12-06

    Applicant: Arm Limited

    Inventor： Emre OZER ,  Jedrzej KUFEL ,  James Edward MYERS ,  Remy POTTIER ,  John Philip BIGGS

    IPC: A41D1/00 ,  G06F1/16 ,  A61F6/04 ,  A41D19/015

    CPC classification number: A41D1/002 ,  G06F1/163 ,  A61F6/04 ,  A41D19/015

    Abstract: Wearable items and methods of monitoring wearable items are disclosed. The wearable item comprises a flexible base material forming at least a portion of the wearable item, plural conductive traces traversing the flexible base material, and conductivity sensing circuitry coupled to the plural conductive traces. The conductivity sensing circuitry is configured to distinguish conductivity from non-conductivity of the plural conductive traces, and configured to generate a conductivity indication for at least one of the plural conductive traces. The plural conductive traces follow indirect paths across the flexible base material, allowing the flexible material to flex and stretch normally without breaking the conductive traces.

    MEMORY CIRCUIT
    18.
    发明申请
    MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20180268885A1

    公开(公告)日：2018-09-20

    申请号：US15762752

    申请日：2016-10-14

    Applicant: ARM LIMITED

    Inventor： James Edward MYERS ,  David William HOWARD ,  John Philip BIGGS

    IPC: G11C11/00

    CPC classification number: G11C11/005 ,  G11C11/40 ,  G11C14/0054 ,  G11C17/12 ,  G11C17/14 ,  G11C17/18 ,  H01L27/12

    Abstract: A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states;a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines;and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array.

    Controlling Voltage Generation and Voltage Comparison
    20.
    发明申请
    Controlling Voltage Generation and Voltage Comparison 有权
    控制电压产生和电压比较

    公开(公告)号：US20160118882A1

    公开(公告)日：2016-04-28

    申请号：US14922783

    申请日：2015-10-26

    Applicant: ARM Limited

    Inventor： Parameshwarappa Anand Kumar SAVANTH ,  James Edward MYERS ,  David Walter FLYNN ,  Bal S. SANDHU

    IPC: H02M3/157 ,  G01R19/00

    CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

    Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

    Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

Patent Agency Ranking