-
公开(公告)号：US20170269960A1
公开(公告)日：2017-09-21
申请号：US15532221
申请日：2015-11-24
Applicant: ARM Limited
Inventor： Stephan DIESTELHORST , Matthew James HORSNELL , Guy LARRI
CPC classification number: G06F9/467 , G06F9/3842 , G06F9/3863
Abstract: An apparatus (2) with multiple processing elements (4, 6, 8) has shared transactional processing resources (10, 50, 75) for supporting processing of transactions, which comprise operations performed speculatively following a transaction start event whose results are committed following a transaction end event. The transactional processing resources may have a significant overhead and sharing these between the processing elements helps reduce energy consumption and circuit area.
-
公开(公告)号：US20160026806A1
公开(公告)日：2016-01-28
申请号：US14792796
申请日：2015-07-07
Applicant: ARM Limited
CPC classification number: G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/12 , H04L2209/125
Abstract: A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
Abstract translation: 数据处理系统包括单指令多数据寄存器文件和单指令多处理电路。 单指令多数据处理电路支持执行用于执行散列算法部分的密码处理指令。 操作数存储在单指令多数据寄存器文件中。 加密支持指令不遵循正常的基于通道的处理，并且生成输出操作数，其中输出操作数的不同部分取决于输入操作数中的多个不同元素。
-
公开(公告)号：US20230325325A1
公开(公告)日：2023-10-12
申请号：US18044499
申请日：2021-08-16
Applicant: Arm Limited
Inventor： Wei WANG , Matthew James HORSNELL
IPC: G06F12/12 , G06F12/0897 , G06F12/0862
CPC classification number: G06F12/12 , G06F2212/601 , G06F12/0862 , G06F12/0897
Abstract: An apparatus has processing circuitry with support for transactional memory, and a cache hierarchy comprising at least two levels of cache. In response to a draining trigger event having potential to cause loss of state stored in at least one further level cache beyond a predetermined level cache in which speculative store data generated by a transaction is marked as speculative until the transaction is committed, draining circuitry performs a draining operation to scan a subset of the cache hierarchy to identify dirty cache lines and write data associated with the dirty cache lines to persistent memory. The subset of the cache hierarchy includes the at least one further level cache. In the draining operation, speculative store data marked as speculative in the predetermined level cache is prevented from being drained to the persistent memory.
-
14.发明申请公开(公告)号：US20210342152A1
公开(公告)日：2021-11-04
申请号：US17255001
申请日：2019-05-09
Applicant: Arm Limited
Inventor： Matthew James HORSNELL , Grigorios MAGKLIS , Richard Roy GRISENTHWAITE , Nathan Yong Seng CHONG
Abstract: An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.
-
公开(公告)号：US20210124585A1
公开(公告)日：2021-04-29
申请号：US16662396
申请日：2019-10-24
Applicant: Arm Limited
Inventor： Roko GRUBISIC , Giacomo GABRIELLI , Matthew James HORSNELL , Syed Ali Mustafa ZAIDI
Abstract: Circuitry comprises decode circuitry to decode program instructions including producer instructions and consumer instructions, a consumer instruction requiring, as an input operand, a result generated by execution of a producer instruction; and execution circuitry to execute the program instructions; in which: the decode circuitry is configured to control operation of the execution circuitry in response to hint data associated with a given producer instruction and indicating, for the given producer instruction, a number of consumer instructions which require, as an input operand, a result generated by the given producer instruction.
-
Patent Agency Ranking
公开(公告)号：US20210103503A1
公开(公告)日：2021-04-08
申请号：US17046396
申请日：2019-04-08
Applicant: Arm Limited
Inventor： Matthew James HORSNELL , Grigorios MAGKLIS , Stephan DIESTELHORST
Abstract: An apparatus and a method of operating a data processing apparatus, and simulators thereof, are disclosed. Data processing circuitry performs data processing operations in response to instructions, where some sets of instructions may be defined as a transaction which are to be performed atomically with respect to other operations performed by the data processing circuitry. When a synchronous exception occurs during a transaction the transaction is aborted and an exception counter is incremented. When the counter reaches a threshold value a transaction failure signal is generated, allowing, if appropriate a response to this number of exceptions causing transaction aborts to be carried out.
-
公开(公告)号：US20200257551A1
公开(公告)日：2020-08-13
申请号：US16651045
申请日：2018-08-21
Applicant: Arm Limited
Inventor： Grigorios MAGKLIS , Matthew James HORSNELL , Stephan DIESTELHORST
Abstract: In a system providing transactional memory support, a transaction nesting depth testing instruction is provided for triggering processing circuitry to set at least one status value to one of a plurality of states depending on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth is and at least one further state selected when the transaction nesting depth is greater than or less than. The ISA supported enables the setting of the at least one status value and a conditional branch conditional on the at least one status value being in the first state to be performed in response to a single transaction nesting depth testing instruction and a single conditional branch instruction.
-
公开(公告)号：US20170017583A1
公开(公告)日：2017-01-19
申请号：US15123805
申请日：2015-03-04
Applicant: ARM LIMITED
CPC classification number: G06F12/1475 , G06F9/467 , G06F2212/1052
Abstract: An asymmetric multiprocessor system (2) includes a plurality of processor cores (4, 6) supporting transactional memory via controllers (14, 16) as well as one or more processor cores 8 which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processing element is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processing element is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processing element is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times. The request may arise through execution of a transaction start instruction which serves to read a lock address from an architectural register (76) storing the lock address should the processor executing that transaction start instruction not already be executing a pending memory transaction. If the processor is already executing a memory transaction, then the transaction start instruction need not access the lock value stored at the lock address held within the lock address register (76) as it may be assumed that the lock value has already been checked.
Abstract translation: 非对称多处理器系统（2）包括经由控制器（14,16）支持事务存储器的多个处理器核心（4,6）以及不经由硬件支持事务存储器的一个或多个处理器核心8。 控制器通过确定其相关联的处理元件当前是否正在执行由在该锁定地址处存储的锁定值保护的存储器事务以及它们的处理元件是否正在执行这样的事务来响应对独占访问锁定地址的请求的接收 ，然后延迟释放用于独占访问的锁定地址，直到满足预定条件。 如果处理元件没有执行这样的保护的存储器事务，则可以无条件地释放锁定地址以进行独占访问。 预定条件可以是从接收到请求和/或先前已经接收到请求并拒绝了阈值次数以来已经超过阈值延迟。 如果处理器执行该事务开始指令还没有执行未完成的存储器事务，则可以通过执行事务开始指令来产生请求，该事务开始指令用于从存储锁定地址的架构寄存器（76）读取锁定地址。 如果处理器已经在执行存储器事务处理，则事务开始指令不需要访问存储在锁定地址寄存器（76）内的锁定地址处的锁定值，因为可以假定已经检查了锁定值。
-
19.发明公开公开(公告)号：US20230280904A1
公开(公告)日：2023-09-07
申请号：US18040577
申请日：2021-08-05
Applicant: Arm Limited
Inventor： Matthew James HORSNELL
IPC: G06F3/06 , G06F12/0815
CPC classification number: G06F3/061 , G06F3/0653 , G06F3/0673 , G06F12/0815
Abstract: An apparatus comprises address storage circuitry to store indications of a first set of memory locations of a shared memory; a capacity indicator to indicate whether a capacity of the address storage circuitry has been reached, and monitoring circuitry to monitor the first set of memory locations and a second set of memory locations of the shared memory, identified in further storage circuitry to identify whether data stored at either set of memory locations has been modified. The monitoring circuitry is responsive to determining that the data has been modified to generate an indication that the data has been modified, and processing circuitry receives the indication and executes a monitor-address instruction specifying an address of a new memory location in the shared memory to update the address storage circuitry or the further storage circuitry to indicate the new address, depending on the capacity indicator.
-
公开(公告)号：US20210141643A1
公开(公告)日：2021-05-13
申请号：US17258287
申请日：2019-05-09
Applicant: Arm Limited
Inventor： Matthew James HORSNELL , Grigorios MAGKLIS , Stephan DIESTELHORST
Abstract: An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry. In response to a transactional compare-and-discard instruction executed within a given transaction, specifying a target address and a compare value, the processing circuitry loads a target data value from a memory location corresponding to the target address; sets at least one condition status indication depending on a result of comparing the target data value and the compare value; and discards the target data value without adding the target address to a working set of addresses tracked for the given transaction. This is useful for enabling thread level speculation to be implemented on a transactional memory architecture.
-
-
-
-
-
-
-
-
-
Search Results
24
records
(took 0.019 seconds)
